Merge branch 'master' into 3.5-release

4 files changed, 362 insertions, 150 deletions

diff --git a/src/test/scala/chiselTests/experimental/hierarchy/Annotations.scala b/src/test/scala/chiselTests/experimental/hierarchy/Annotations.scala
index eba412f1..2c1d2e9e 100644
--- a/src/test/scala/chiselTests/experimental/hierarchy/Annotations.scala
+++ b/src/test/scala/chiselTests/experimental/hierarchy/Annotations.scala
@@ -5,20 +5,22 @@ package chiselTests.experimental.hierarchy
 import _root_.firrtl.annotations._
 import chisel3.experimental.{annotate, BaseModule}
 import chisel3.Data
-import chisel3.experimental.hierarchy.{Instance, Definition, Hierarchy}
+import chisel3.experimental.hierarchy.{Definition, Hierarchy, Instance}
 
 object Annotations {
   case class MarkAnnotation(target: IsMember, tag: String) extends SingleTargetAnnotation[IsMember] {
     def duplicate(n: IsMember): Annotation = this.copy(target = n)
   }
-  case class MarkChiselHierarchyAnnotation[B <: BaseModule](d: Hierarchy[B], tag: String, isAbsolute: Boolean) extends chisel3.experimental.ChiselAnnotation {
+  case class MarkChiselHierarchyAnnotation[B <: BaseModule](d: Hierarchy[B], tag: String, isAbsolute: Boolean)
+      extends chisel3.experimental.ChiselAnnotation {
     def toFirrtl = MarkAnnotation(d.toTarget, tag)
   }
-  case class MarkChiselAnnotation(d: Data, tag: String, isAbsolute: Boolean) extends chisel3.experimental.ChiselAnnotation {
-    def toFirrtl = if(isAbsolute) MarkAnnotation(d.toAbsoluteTarget, tag) else MarkAnnotation(d.toTarget, tag)
+  case class MarkChiselAnnotation(d: Data, tag: String, isAbsolute: Boolean)
+      extends chisel3.experimental.ChiselAnnotation {
+    def toFirrtl = if (isAbsolute) MarkAnnotation(d.toAbsoluteTarget, tag) else MarkAnnotation(d.toTarget, tag)
   }
-  def mark(d: Data, tag: String): Unit = annotate(MarkChiselAnnotation(d, tag, false))
-  def mark[B <: BaseModule](d: Hierarchy[B], tag: String): Unit = annotate(MarkChiselHierarchyAnnotation(d, tag, true))
-  def amark(d: Data, tag: String): Unit = annotate(MarkChiselAnnotation(d, tag, true))
+  def mark(d:                   Data, tag:         String): Unit = annotate(MarkChiselAnnotation(d, tag, false))
+  def mark[B <: BaseModule](d:  Hierarchy[B], tag: String): Unit = annotate(MarkChiselHierarchyAnnotation(d, tag, true))
+  def amark(d:                  Data, tag:         String): Unit = annotate(MarkChiselAnnotation(d, tag, true))
   def amark[B <: BaseModule](d: Hierarchy[B], tag: String): Unit = annotate(MarkChiselHierarchyAnnotation(d, tag, true))
 }
diff --git a/src/test/scala/chiselTests/experimental/hierarchy/DefinitionSpec.scala b/src/test/scala/chiselTests/experimental/hierarchy/DefinitionSpec.scala
index f33f7869..63beb394 100644
--- a/src/test/scala/chiselTests/experimental/hierarchy/DefinitionSpec.scala
+++ b/src/test/scala/chiselTests/experimental/hierarchy/DefinitionSpec.scala
@@ -5,7 +5,7 @@ package experimental.hierarchy
 
 import chisel3._
 import chisel3.experimental.BaseModule
-import chisel3.experimental.hierarchy.{Definition, Instance, instantiable, public}
+import chisel3.experimental.hierarchy.{instantiable, public, Definition, Instance}
 
 // TODO/Notes
 // - In backport, clock/reset are not automatically assigned. I think this is fixed in 3.5
@@ -19,7 +19,7 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
         val definition = Definition(new AddOne)
       }
       val (chirrtl, _) = getFirrtlAndAnnos(new Top)
-      chirrtl.serialize should include ("module AddOne :")
+      chirrtl.serialize should include("module AddOne :")
     }
     it("0.2: accessing internal fields through non-generated means is hard to do") {
       class Top extends Module {
@@ -29,7 +29,7 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
         definition.in
       }
       val (chirrtl, _) = getFirrtlAndAnnos(new Top)
-      chirrtl.serialize should include ("module AddOne :")
+      chirrtl.serialize should include("module AddOne :")
     }
     it("0.2: reset inference is not defaulted to Bool for definitions") {
       class Top extends Module with RequireAsyncReset {
@@ -38,21 +38,27 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
         i0.in := 0.U
       }
       val (chirrtl, _) = getFirrtlAndAnnos(new Top)
-      chirrtl.serialize should include ("inst i0 of HasUninferredReset")
+      chirrtl.serialize should include("inst i0 of HasUninferredReset")
     }
     it("0.3: module names of repeated definition should be sequential") {
       class Top extends Module {
-        val k = Module(new AddTwoParameterized(4, (x: Int) => Seq.tabulate(x){j =>
-          val addOneDef = Definition(new AddOneParameterized(x+j))
-          val addOne = Instance(addOneDef)
-          addOne
-        }))
+        val k = Module(
+          new AddTwoParameterized(
+            4,
+            (x: Int) =>
+              Seq.tabulate(x) { j =>
+                val addOneDef = Definition(new AddOneParameterized(x + j))
+                val addOne = Instance(addOneDef)
+                addOne
+              }
+          )
+        )
       }
       val (chirrtl, _) = getFirrtlAndAnnos(new Top)
-      chirrtl.serialize should include ("module AddOneParameterized :")
-      chirrtl.serialize should include ("module AddOneParameterized_1 :")
-      chirrtl.serialize should include ("module AddOneParameterized_2 :")
-      chirrtl.serialize should include ("module AddOneParameterized_3 :")
+      chirrtl.serialize should include("module AddOneParameterized :")
+      chirrtl.serialize should include("module AddOneParameterized_1 :")
+      chirrtl.serialize should include("module AddOneParameterized_2 :")
+      chirrtl.serialize should include("module AddOneParameterized_3 :")
     }
     it("0.4: multiple instantiations should have sequential names") {
       class Top extends Module {
@@ -61,22 +67,28 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
         val otherAddOne = Module(new AddOneParameterized(4))
       }
       val (chirrtl, _) = getFirrtlAndAnnos(new Top)
-      chirrtl.serialize should include ("module AddOneParameterized :")
-      chirrtl.serialize should include ("module AddOneParameterized_1 :")
+      chirrtl.serialize should include("module AddOneParameterized :")
+      chirrtl.serialize should include("module AddOneParameterized_1 :")
     }
     it("0.5: nested definitions should have sequential names") {
       class Top extends Module {
-        val k = Module(new AddTwoWithNested(4, (x: Int) => Seq.tabulate(x){j =>
-          val addOneDef = Definition(new AddOneWithNested(x+j))
-          val addOne = Instance(addOneDef)
-          addOne
-        }))
+        val k = Module(
+          new AddTwoWithNested(
+            4,
+            (x: Int) =>
+              Seq.tabulate(x) { j =>
+                val addOneDef = Definition(new AddOneWithNested(x + j))
+                val addOne = Instance(addOneDef)
+                addOne
+              }
+          )
+        )
       }
       val (chirrtl, _) = getFirrtlAndAnnos(new Top)
-      chirrtl.serialize should include ("module AddOneWithNested :")
-      chirrtl.serialize should include ("module AddOneWithNested_1 :")
-      chirrtl.serialize should include ("module AddOneWithNested_2 :")
-      chirrtl.serialize should include ("module AddOneWithNested_3 :")
+      chirrtl.serialize should include("module AddOneWithNested :")
+      chirrtl.serialize should include("module AddOneWithNested_1 :")
+      chirrtl.serialize should include("module AddOneWithNested_2 :")
+      chirrtl.serialize should include("module AddOneWithNested_3 :")
     }
   }
   describe("1: Annotations on definitions in same chisel compilation") {
@@ -179,7 +191,7 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
       val (_, annos) = getFirrtlAndAnnos(new Top)
       annos should contain(MarkAnnotation("~Top|AddOneWithInstantiableInstantiable/i0:AddOne".it, "i0.i0"))
     }
-    it("1.10: should work for targets on definition to have correct circuit name"){
+    it("1.10: should work for targets on definition to have correct circuit name") {
       class Top extends Module {
         val definition = Definition(new AddOneWithAnnotation)
       }
@@ -307,6 +319,16 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
       val (_, annos) = getFirrtlAndAnnos(new Top)
       annos should contain(MarkAnnotation("~Top|ConcreteHasBlah".mt, "10"))
     }
+    it("3.11: should work on eithers") {
+      class Top() extends Module {
+        val i = Definition(new HasEither())
+        i.x.map(x => mark(x, "xright")).left.map(x => mark(x, "xleft"))
+        i.y.map(x => mark(x, "yright")).left.map(x => mark(x, "yleft"))
+      }
+      val (_, annos) = getFirrtlAndAnnos(new Top)
+      annos should contain(MarkAnnotation("~Top|HasEither>x".rt, "xright"))
+      annos should contain(MarkAnnotation("~Top|HasEither>y".rt, "yleft"))
+    }
   }
   describe("4: toDefinition") {
     it("4.0: should work on modules") {
@@ -401,10 +423,12 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
       )
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
-    it("6.1 An @instantiable Module that implements an @instantiable trait should be able to use extension methods from both") {
+    it(
+      "6.1 An @instantiable Module that implements an @instantiable trait should be able to use extension methods from both"
+    ) {
       class Top extends Module {
         val i: Definition[ModuleWithCommonIntf] = Definition(new ModuleWithCommonIntf)
         mark(i.io.in, "gotcha")
@@ -418,7 +442,7 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
       )
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
     it("6.2 A BlackBox that implements an @instantiable trait should be instantiable as that trait") {
@@ -434,7 +458,7 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
       )
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
     it("6.3 It should be possible to have Vectors of @instantiable traits mixing concrete subclasses") {
@@ -456,7 +480,7 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
       )
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
   }
@@ -495,10 +519,10 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       val text = chirrtl.serialize
       for (line <- expectedLines) {
-        text should include (line)
+        text should include(line)
       }
       for (e <- expectedAnnos.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
     ignore("7.1: should work on Aggregate Views that are mapped 1:1") {
@@ -523,7 +547,7 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
       }
       val expectedAnnos = List(
         "~Top|MyModule>a".rt -> "in",
-        "~Top|MyModule>a.foo".rt -> "in_bar",
+        "~Top|MyModule>a.foo".rt -> "in_bar"
       )
       val expectedLines = List(
         "i.a <= foo",
@@ -532,10 +556,10 @@ class DefinitionSpec extends ChiselFunSpec with Utils {
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       val text = chirrtl.serialize
       for (line <- expectedLines) {
-        text should include (line)
+        text should include(line)
       }
       for (e <- expectedAnnos.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
   }
diff --git a/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala b/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala
index c0f504ff..5b78b7cc 100644
--- a/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala
+++ b/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala
@@ -11,7 +11,7 @@ object Examples {
   import Annotations._
   @instantiable
   class AddOne extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     @public val innerWire = Wire(UInt(32.W))
     innerWire := in + 1.U
@@ -19,7 +19,7 @@ object Examples {
   }
   @instantiable
   class AddOneWithAnnotation extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     @public val innerWire = Wire(UInt(32.W))
     mark(innerWire, "innerWire")
@@ -28,7 +28,7 @@ object Examples {
   }
   @instantiable
   class AddOneWithAbsoluteAnnotation extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     @public val innerWire = Wire(UInt(32.W))
     amark(innerWire, "innerWire")
@@ -37,12 +37,12 @@ object Examples {
   }
   @instantiable
   class AddOneParameterized(width: Int) extends Module {
-    @public val in  = IO(Input(UInt(width.W)))
+    @public val in = IO(Input(UInt(width.W)))
     @public val out = IO(Output(UInt(width.W)))
     out := in + 1.U
   }
   class AddOneWithNested(width: Int) extends Module {
-    @public val in  = IO(Input(UInt(width.W)))
+    @public val in = IO(Input(UInt(width.W)))
     @public val out = IO(Output(UInt(width.W)))
     val addOneDef = Seq.fill(3)(Definition(new AddOne))
     out := in + 1.U
@@ -50,7 +50,7 @@ object Examples {
 
   @instantiable
   class AddTwo extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     @public val definition = Definition(new AddOne)
     @public val i0: Instance[AddOne] = Instance(definition)
@@ -61,7 +61,7 @@ object Examples {
   }
   @instantiable
   class AddTwoMixedModules extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     val definition = Definition(new AddOne)
     @public val i0: Instance[AddOne] = Instance(definition)
@@ -71,24 +71,25 @@ object Examples {
     out := i1.out
   }
   @instantiable
-  class AddTwoParameterized(width: Int, makeParameterizedOnes: Int => Seq[Instance[AddOneParameterized]]) extends Module {
-    val in  = IO(Input(UInt(width.W)))
+  class AddTwoParameterized(width: Int, makeParameterizedOnes: Int => Seq[Instance[AddOneParameterized]])
+      extends Module {
+    val in = IO(Input(UInt(width.W)))
     val out = IO(Output(UInt(width.W)))
     val addOnes = makeParameterizedOnes(width)
     addOnes.head.in := in
     out := addOnes.last.out
-    addOnes.zip(addOnes.tail).foreach{ case (head, tail) => tail.in := head.out}
+    addOnes.zip(addOnes.tail).foreach { case (head, tail) => tail.in := head.out }
   }
   @instantiable
   class AddTwoWithNested(width: Int, makeParameterizedOnes: Int => Seq[Instance[AddOneWithNested]]) extends Module {
-    val in  = IO(Input(UInt(width.W)))
+    val in = IO(Input(UInt(width.W)))
     val out = IO(Output(UInt(width.W)))
     val addOnes = makeParameterizedOnes(width)
   }
 
   @instantiable
   class AddFour extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     @public val definition = Definition(new AddTwoMixedModules)
     @public val i0 = Instance(definition)
@@ -111,7 +112,7 @@ object Examples {
   }
   @instantiable
   class AddOneWithInstantiableWire extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     @public val wireContainer = new WireContainer()
     wireContainer.innerWire := in + 1.U
@@ -123,7 +124,7 @@ object Examples {
   }
   @instantiable
   class AddOneWithInstantiableModule extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     @public val moduleContainer = new AddOneContainer()
     moduleContainer.i0.in := in
@@ -136,7 +137,7 @@ object Examples {
   }
   @instantiable
   class AddOneWithInstantiableInstance extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     @public val instanceContainer = new AddOneInstanceContainer()
     instanceContainer.i0.in := in
@@ -148,7 +149,7 @@ object Examples {
   }
   @instantiable
   class AddOneWithInstantiableInstantiable extends Module {
-    @public val in  = IO(Input(UInt(32.W)))
+    @public val in = IO(Input(UInt(32.W)))
     @public val out = IO(Output(UInt(32.W)))
     @public val containerContainer = new AddOneContainerContainer()
     containerContainer.container.i0.in := in
@@ -157,12 +158,12 @@ object Examples {
   @instantiable
   class Viewer(val y: AddTwo, markPlease: Boolean) {
     @public val x = y
-    if(markPlease) mark(x.i0.innerWire, "first")
+    if (markPlease) mark(x.i0.innerWire, "first")
   }
   @instantiable
   class ViewerParent(val x: AddTwo, markHere: Boolean, markThere: Boolean) extends Module {
     @public val viewer = new Viewer(x, markThere)
-    if(markHere) mark(viewer.x.i0.innerWire, "second")
+    if (markHere) mark(viewer.x.i0.innerWire, "second")
   }
   @instantiable
   class MultiVal() extends Module {
@@ -194,6 +195,11 @@ object Examples {
     @public val x: Option[UInt] = Some(Wire(UInt(3.W)))
   }
   @instantiable
+  class HasEither() extends Module {
+    @public val x: Either[Bool, UInt] = Right(Wire(UInt(3.W)).suggestName("x"))
+    @public val y: Either[Bool, UInt] = Left(Wire(Bool()).suggestName("y"))
+  }
+  @instantiable
   class HasVec() extends Module {
     @public val x = VecInit(1.U, 2.U, 3.U)
   }
@@ -236,4 +242,14 @@ object Examples {
   class HasTypeParams[D <: Data](d: D) extends Module {
     @public val blah = Wire(d)
   }
+
+  @instantiable
+  class HasMultipleTypeParamsInside extends Module {
+    val tpDef0 = Definition(new HasTypeParams(Bool()))
+    val tpDef1 = Definition(new HasTypeParams(UInt(4.W)))
+    val i00 = Instance(tpDef0)
+    val i01 = Instance(tpDef0)
+    val i10 = Instance(tpDef1)
+    val i11 = Instance(tpDef1)
+  }
 }
diff --git a/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala b/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala
index 9ceb9b40..f62d1e49 100644
--- a/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala
+++ b/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala
@@ -5,10 +5,9 @@ package experimental.hierarchy
 
 import chisel3._
 import chisel3.experimental.BaseModule
-import chisel3.experimental.hierarchy.{Definition, Instance, instantiable, public}
+import chisel3.experimental.hierarchy.{instantiable, public, Definition, Instance}
 import chisel3.util.{DecoupledIO, Valid}
 
-
 // TODO/Notes
 // - In backport, clock/reset are not automatically assigned. I think this is fixed in 3.5
 // - CircuitTarget for annotations on the definition are wrong - needs to be fixed.
@@ -22,7 +21,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         val i0 = Instance(definition)
       }
       val (chirrtl, _) = getFirrtlAndAnnos(new Top)
-      chirrtl.serialize should include ("inst i0 of AddOne")
+      chirrtl.serialize should include("inst i0 of AddOne")
     }
     it("0.1: name of an instanceclone should not error") {
       class Top extends Module {
@@ -31,7 +30,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         val i = i0.i0 // This should not error
       }
       val (chirrtl, _) = getFirrtlAndAnnos(new Top)
-      chirrtl.serialize should include ("inst i0 of AddTwo")
+      chirrtl.serialize should include("inst i0 of AddTwo")
     }
     it("0.2: accessing internal fields through non-generated means is hard to do") {
       class Top extends Module {
@@ -42,63 +41,63 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         i0.in
       }
       val (chirrtl, _) = getFirrtlAndAnnos(new Top)
-      chirrtl.serialize should include ("inst i0 of AddOne")
+      chirrtl.serialize should include("inst i0 of AddOne")
     }
   }
   describe("1: Annotations on instances in same chisel compilation") {
     it("1.0: should work on a single instance, annotating the instance") {
       class Top extends Module {
         val definition: Definition[AddOne] = Definition(new AddOne)
-        val i0: Instance[AddOne] = Instance(definition)
+        val i0:         Instance[AddOne] = Instance(definition)
         mark(i0, "i0")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddOne".it, "i0"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddOne".it, "i0"))
     }
     it("1.1: should work on a single instance, annotating an inner wire") {
       class Top extends Module {
         val definition: Definition[AddOne] = Definition(new AddOne)
-        val i0: Instance[AddOne] = Instance(definition)
+        val i0:         Instance[AddOne] = Instance(definition)
         mark(i0.innerWire, "i0.innerWire")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddOne>innerWire".rt, "i0.innerWire"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddOne>innerWire".rt, "i0.innerWire"))
     }
     it("1.2: should work on a two nested instances, annotating the instance") {
       class Top extends Module {
         val definition: Definition[AddTwo] = Definition(new AddTwo)
-        val i0: Instance[AddTwo] = Instance(definition)
+        val i0:         Instance[AddTwo] = Instance(definition)
         mark(i0.i0, "i0.i0")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddTwo/i0:AddOne".it, "i0.i0"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddTwo/i0:AddOne".it, "i0.i0"))
     }
     it("1.3: should work on a two nested instances, annotating the inner wire") {
       class Top extends Module {
         val definition: Definition[AddTwo] = Definition(new AddTwo)
-        val i0: Instance[AddTwo] = Instance(definition)
+        val i0:         Instance[AddTwo] = Instance(definition)
         mark(i0.i0.innerWire, "i0.i0.innerWire")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddTwo/i0:AddOne>innerWire".rt, "i0.i0.innerWire"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddTwo/i0:AddOne>innerWire".rt, "i0.i0.innerWire"))
     }
     it("1.4: should work on a nested module in an instance, annotating the module") {
       class Top extends Module {
         val definition: Definition[AddTwoMixedModules] = Definition(new AddTwoMixedModules)
-        val i0: Instance[AddTwoMixedModules] = Instance(definition)
+        val i0:         Instance[AddTwoMixedModules] = Instance(definition)
         mark(i0.i1, "i0.i1")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddTwoMixedModules/i1:AddOne_1".it, "i0.i1"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddTwoMixedModules/i1:AddOne_1".it, "i0.i1"))
     }
     it("1.5: should work on an instantiable container, annotating a wire") {
       class Top extends Module {
         val definition: Definition[AddOneWithInstantiableWire] = Definition(new AddOneWithInstantiableWire)
-        val i0: Instance[AddOneWithInstantiableWire] = Instance(definition)
+        val i0:         Instance[AddOneWithInstantiableWire] = Instance(definition)
         mark(i0.wireContainer.innerWire, "i0.innerWire")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableWire>innerWire".rt, "i0.innerWire"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableWire>innerWire".rt, "i0.innerWire"))
     }
     it("1.6: should work on an instantiable container, annotating a module") {
       class Top extends Module {
@@ -107,7 +106,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         mark(i0.moduleContainer.i0, "i0.i0")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableModule/i0:AddOne".it, "i0.i0"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableModule/i0:AddOne".it, "i0.i0"))
     }
     it("1.7: should work on an instantiable container, annotating an instance") {
       class Top extends Module {
@@ -116,7 +115,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         mark(i0.instanceContainer.i0, "i0.i0")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableInstance/i0:AddOne".it, "i0.i0"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableInstance/i0:AddOne".it, "i0.i0"))
     }
     it("1.8: should work on an instantiable container, annotating an instantiable container's module") {
       class Top extends Module {
@@ -125,7 +124,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         mark(i0.containerContainer.container.i0, "i0.i0")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableInstantiable/i0:AddOne".it, "i0.i0"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableInstantiable/i0:AddOne".it, "i0.i0"))
     }
     it("1.9: should work on public member which references public member of another instance") {
       class Top extends Module {
@@ -134,24 +133,24 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         mark(i0.containerContainer.container.i0, "i0.i0")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableInstantiable/i0:AddOne".it, "i0.i0"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:AddOneWithInstantiableInstantiable/i0:AddOne".it, "i0.i0"))
     }
-    it("1.10: should work for targets on definition to have correct circuit name"){
+    it("1.10: should work for targets on definition to have correct circuit name") {
       class Top extends Module {
         val definition = Definition(new AddOneWithAnnotation)
         val i0 = Instance(definition)
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|AddOneWithAnnotation>innerWire".rt, "innerWire"))
+      annos should contain(MarkAnnotation("~Top|AddOneWithAnnotation>innerWire".rt, "innerWire"))
     }
-    it("1.11: should work on things with type parameters"){
+    it("1.11: should work on things with type parameters") {
       class Top extends Module {
         val definition = Definition(new HasTypeParams[UInt](UInt(3.W)))
         val i0 = Instance(definition)
         mark(i0.blah, "blah")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/i0:HasTypeParams>blah".rt, "blah"))
+      annos should contain(MarkAnnotation("~Top|Top/i0:HasTypeParams>blah".rt, "blah"))
     }
   }
   describe("2: Annotations on designs not in the same chisel compilation") {
@@ -161,7 +160,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         val parent = Instance(Definition(new ViewerParent(x, false, true)))
       }
       val (_, annos) = getFirrtlAndAnnos(new Top(first))
-      annos should contain (MarkAnnotation("~AddTwo|AddTwo/i0:AddOne>innerWire".rt, "first"))
+      annos should contain(MarkAnnotation("~AddTwo|AddTwo/i0:AddOne>innerWire".rt, "first"))
     }
     it("2.1: should work on an innerWire, marked in a different compilation, in instanced instantiable") {
       val first = elaborateAndGetModule(new AddTwo)
@@ -169,7 +168,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         val parent = Instance(Definition(new ViewerParent(x, true, false)))
       }
       val (_, annos) = getFirrtlAndAnnos(new Top(first))
-      annos should contain (MarkAnnotation("~AddTwo|AddTwo/i0:AddOne>innerWire".rt, "second"))
+      annos should contain(MarkAnnotation("~AddTwo|AddTwo/i0:AddOne>innerWire".rt, "second"))
     }
     it("2.2: should work on an innerWire, marked in a different compilation, in instanced module") {
       val first = elaborateAndGetModule(new AddTwo)
@@ -178,7 +177,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         mark(parent.viewer.x.i0.innerWire, "third")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top(first))
-      annos should contain (MarkAnnotation("~AddTwo|AddTwo/i0:AddOne>innerWire".rt, "third"))
+      annos should contain(MarkAnnotation("~AddTwo|AddTwo/i0:AddOne>innerWire".rt, "third"))
     }
   }
   describe("3: @public") {
@@ -188,7 +187,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         mark(mv.x, "mv.x")
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/mv:MultiVal>x".rt, "mv.x"))
+      annos should contain(MarkAnnotation("~Top|Top/mv:MultiVal>x".rt, "mv.x"))
     }
     it("3.1: should work on lazy vals") {
       class Top() extends Module {
@@ -196,7 +195,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         mark(lv.x, lv.y)
       }
       val (_, annos) = getFirrtlAndAnnos(new Top)
-      annos should contain (MarkAnnotation("~Top|Top/lv:LazyVal>x".rt, "Hi"))
+      annos should contain(MarkAnnotation("~Top|Top/lv:LazyVal>x".rt, "Hi"))
     }
     it("3.2: should work on islookupables") {
       class Top() extends Module {
@@ -275,10 +274,10 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       val text = chirrtl.serialize
       for (line <- lines) {
-        text should include (line)
+        text should include(line)
       }
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
     ignore("3.10: should work on vals in constructor arguments") {
@@ -289,6 +288,16 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       val (_, annos) = getFirrtlAndAnnos(new Top)
       annos should contain(MarkAnnotation("~Top|Top/i:HasPublicConstructorArgs>x".rt, "10"))
     }
+    it("3.11: should work on eithers") {
+      class Top() extends Module {
+        val i = Instance(Definition(new HasEither()))
+        i.x.map(x => mark(x, "xright")).left.map(x => mark(x, "xleft"))
+        i.y.map(x => mark(x, "yright")).left.map(x => mark(x, "yleft"))
+      }
+      val (_, annos) = getFirrtlAndAnnos(new Top)
+      annos should contain(MarkAnnotation("~Top|Top/i:HasEither>x".rt, "xright"))
+      annos should contain(MarkAnnotation("~Top|Top/i:HasEither>y".rt, "yleft"))
+    }
   }
   describe("4: toInstance") {
     it("4.0: should work on modules") {
@@ -398,7 +407,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       val (_, annos) = getFirrtlAndAnnos(new Top)
       annos should contain(MarkAnnotation("~Top|Top/i:AddTwo/i1:AddOne".it, "blah"))
     }
-    it("5.6: should work for absolute targets on definition to have correct circuit name"){
+    it("5.6: should work for absolute targets on definition to have correct circuit name") {
       class Top extends Module {
         val definition = Definition(new AddOneWithAbsoluteAnnotation)
         val i0 = Instance(definition)
@@ -437,10 +446,12 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       )
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
-    it("6.1 An @instantiable Module that implements an @instantiable trait should be able to use extension methods from both") {
+    it(
+      "6.1 An @instantiable Module that implements an @instantiable trait should be able to use extension methods from both"
+    ) {
       class Top extends Module {
         val i: Instance[ModuleWithCommonIntf] = Instance(Definition(new ModuleWithCommonIntf))
         mark(i.io.in, "gotcha")
@@ -454,7 +465,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       )
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
     it("6.2 A BlackBox that implements an @instantiable trait should be instantiable as that trait") {
@@ -469,7 +480,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       )
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
     it("6.3 It should be possible to have Vectors of @instantiable traits mixing concrete subclasses") {
@@ -491,7 +502,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       )
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
   }
@@ -530,10 +541,10 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       val text = chirrtl.serialize
       for (line <- expectedLines) {
-        text should include (line)
+        text should include(line)
       }
       for (e <- expectedAnnos.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
 
@@ -578,15 +589,15 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         "bar.valid <= i.b.valid",
         "i.b.ready <= bar.ready",
         "bar.bits.fizz <= i.b.fizz",
-        "bar.bits.buzz <= i.b.buzz",
+        "bar.bits.buzz <= i.b.buzz"
       )
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       val text = chirrtl.serialize
       for (line <- expectedLines) {
-        text should include (line)
+        text should include(line)
       }
       for (e <- expectedAnnos.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
 
@@ -612,7 +623,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       }
       val expected = List(
         "~Top|Top/i:MyModule>a".rt -> "in",
-        "~Top|Top/i:MyModule>b.foo".rt -> "out_bar",
+        "~Top|Top/i:MyModule>b.foo".rt -> "out_bar"
       )
       val lines = List(
         "i.a <= foo",
@@ -621,10 +632,10 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       val text = chirrtl.serialize
       for (line <- lines) {
-        text should include (line)
+        text should include(line)
       }
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
 
@@ -647,7 +658,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       val expected = List(
         // Not 1:1 so will get split out
         "~Top|Top/i:MyModule>a".rt -> "i.ports",
-        "~Top|Top/i:MyModule>b".rt -> "i.ports",
+        "~Top|Top/i:MyModule>b".rt -> "i.ports"
       )
       val lines = List(
         "i.a <= foo",
@@ -656,10 +667,10 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
       val text = chirrtl.serialize
       for (line <- lines) {
-        text should include (line)
+        text should include(line)
       }
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
   }
@@ -682,11 +693,10 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       val expected = List(
         "~Top|HasCMAR/c:AggregatePortModule>io".rt -> "c.io",
         "~Top|HasCMAR/c:AggregatePortModule>io.out".rt -> "c.io.out"
-
       )
       val (_, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
     it("8.1: it should support @public on a CMAR Record in Instances") {
@@ -706,11 +716,10 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       val expected = List(
         "~Top|Top/i:HasCMAR/c:AggregatePortModule>io".rt -> "i.c.io",
         "~Top|Top/i:HasCMAR/c:AggregatePortModule>io.out".rt -> "i.c.io.out"
-
       )
       val (_, annos) = getFirrtlAndAnnos(new Top)
       for (e <- expected.map(MarkAnnotation.tupled)) {
-        annos should contain (e)
+        annos should contain(e)
       }
     }
   }
@@ -754,15 +763,27 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       }
       getFirrtlAndAnnos(new Top)
     }
+    it("9.3 it should ignore type parameters (even though it would be nice if it didn't)") {
+      class Top extends Module {
+        val d0: Definition[Module] = Definition(new HasTypeParams(Bool()))
+        require(d0.isA[HasTypeParams[Bool]])
+        require(d0.isA[HasTypeParams[_]])
+        require(d0.isA[HasTypeParams[UInt]])
+        require(!d0.isA[HasBlah])
+      }
+      getFirrtlAndAnnos(new Top)
+    }
   }
   describe("10: Select APIs") {
     it("10.0: instancesOf") {
       val aspect = aop.inspecting.InspectingAspect({ m: AddTwoMixedModules =>
         val targets = aop.Select.instancesOf[AddOne](m.toDefinition).map { i: Instance[AddOne] => i.toTarget }
-        targets should be (Seq(
-          "~AddTwoMixedModules|AddTwoMixedModules/i0:AddOne".it,
-          "~AddTwoMixedModules|AddTwoMixedModules/i1:AddOne_1".it,
-        ))
+        targets should be(
+          Seq(
+            "~AddTwoMixedModules|AddTwoMixedModules/i0:AddOne".it,
+            "~AddTwoMixedModules|AddTwoMixedModules/i1:AddOne_1".it
+          )
+        )
       })
       getFirrtlAndAnnos(new AddTwoMixedModules, Seq(aspect))
     }
@@ -771,14 +792,18 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         val insts = aop.Select.instancesIn(m.toDefinition)
         val abs = insts.map { i: Instance[BaseModule] => i.toAbsoluteTarget }
         val rel = insts.map { i: Instance[BaseModule] => i.toTarget }
-        abs should be (Seq(
-          "~AddTwoMixedModules|AddTwoMixedModules/i0:AddOne".it,
-          "~AddTwoMixedModules|AddTwoMixedModules/i1:AddOne_1".it,
-        ))
-        rel should be (Seq(
-          "~AddTwoMixedModules|AddTwoMixedModules/i0:AddOne".it,
-          "~AddTwoMixedModules|AddTwoMixedModules/i1:AddOne_1".it,
-        ))
+        abs should be(
+          Seq(
+            "~AddTwoMixedModules|AddTwoMixedModules/i0:AddOne".it,
+            "~AddTwoMixedModules|AddTwoMixedModules/i1:AddOne_1".it
+          )
+        )
+        rel should be(
+          Seq(
+            "~AddTwoMixedModules|AddTwoMixedModules/i0:AddOne".it,
+            "~AddTwoMixedModules|AddTwoMixedModules/i1:AddOne_1".it
+          )
+        )
       })
       getFirrtlAndAnnos(new AddTwoMixedModules, Seq(aspect))
     }
@@ -787,48 +812,58 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         val insts = aop.Select.allInstancesOf[AddOne](m.toDefinition)
         val abs = insts.map { i: Instance[AddOne] => i.in.toAbsoluteTarget }
         val rel = insts.map { i: Instance[AddOne] => i.in.toTarget }
-        rel should be (Seq(
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>in".rt,
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>in".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>in".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>in".rt,
-        ))
-        abs should be (Seq(
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>in".rt,
-          "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>in".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>in".rt,
-          "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>in".rt,
-        ))
+        rel should be(
+          Seq(
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>in".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>in".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>in".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>in".rt
+          )
+        )
+        abs should be(
+          Seq(
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>in".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>in".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>in".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>in".rt
+          )
+        )
       })
       getFirrtlAndAnnos(new AddFour, Seq(aspect))
     }
     it("10.3: definitionsOf") {
       val aspect = aop.inspecting.InspectingAspect({ m: AddTwoMixedModules =>
         val targets = aop.Select.definitionsOf[AddOne](m.toDefinition).map { i: Definition[AddOne] => i.in.toTarget }
-        targets should be (Seq(
-          "~AddTwoMixedModules|AddOne>in".rt,
-          "~AddTwoMixedModules|AddOne_1>in".rt,
-        ))
+        targets should be(
+          Seq(
+            "~AddTwoMixedModules|AddOne>in".rt,
+            "~AddTwoMixedModules|AddOne_1>in".rt
+          )
+        )
       })
       getFirrtlAndAnnos(new AddTwoMixedModules, Seq(aspect))
     }
     it("10.4: definitionsIn") {
       val aspect = aop.inspecting.InspectingAspect({ m: AddTwoMixedModules =>
         val targets = aop.Select.definitionsIn(m.toDefinition).map { i: Definition[BaseModule] => i.toTarget }
-        targets should be (Seq(
-          "~AddTwoMixedModules|AddOne".mt,
-          "~AddTwoMixedModules|AddOne_1".mt,
-        ))
+        targets should be(
+          Seq(
+            "~AddTwoMixedModules|AddOne".mt,
+            "~AddTwoMixedModules|AddOne_1".mt
+          )
+        )
       })
       getFirrtlAndAnnos(new AddTwoMixedModules, Seq(aspect))
     }
     it("10.5: allDefinitionsOf") {
       val aspect = aop.inspecting.InspectingAspect({ m: AddFour =>
         val targets = aop.Select.allDefinitionsOf[AddOne](m.toDefinition).map { i: Definition[AddOne] => i.in.toTarget }
-        targets should be (Seq(
-          "~AddFour|AddOne>in".rt,
-          "~AddFour|AddOne_1>in".rt,
-        ))
+        targets should be(
+          Seq(
+            "~AddFour|AddOne>in".rt,
+            "~AddFour|AddOne_1>in".rt
+          )
+        )
       })
       getFirrtlAndAnnos(new AddFour, Seq(aspect))
     }
@@ -850,6 +885,141 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       })
       intercept[Exception] { getFirrtlAndAnnos(new AddFour, Seq(aspect)) }
     }
+    it("10.9: allInstancesOf.ios") {
+      val aspect = aop.inspecting.InspectingAspect({ m: AddFour =>
+        val abs = aop.Select.allInstancesOf[AddOne](m.toDefinition).flatMap { i: Instance[AddOne] =>
+          aop.Select.ios(i).map(_.toAbsoluteTarget)
+        }
+        val rel = aop.Select.allInstancesOf[AddOne](m.toDefinition).flatMap { i: Instance[AddOne] =>
+          aop.Select.ios(i).map(_.toTarget)
+        }
+        abs should be(
+          Seq(
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>clock".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>reset".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>in".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>out".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>clock".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>reset".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>in".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>out".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>clock".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>reset".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>in".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>out".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>clock".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>reset".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>in".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>out".rt
+          )
+        )
+
+        rel should be(
+          Seq(
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>clock".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>reset".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>in".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i0:AddOne>out".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>clock".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>reset".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>in".rt,
+            "~AddFour|AddFour/i0:AddTwoMixedModules/i1:AddOne_1>out".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>clock".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>reset".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>in".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i0:AddOne>out".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>clock".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>reset".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>in".rt,
+            "~AddFour|AddFour/i1:AddTwoMixedModules/i1:AddOne_1>out".rt
+          )
+        )
+      })
+      getFirrtlAndAnnos(new AddFour, Seq(aspect))
+    }
+    it("10.10: allDefinitionsOf.ios") {
+      val aspect = aop.inspecting.InspectingAspect({ m: AddFour =>
+        val abs = aop.Select.allDefinitionsOf[AddOne](m.toDefinition).flatMap { i: Definition[AddOne] =>
+          aop.Select.ios(i).map(_.toAbsoluteTarget)
+        }
+        val rel = aop.Select.allDefinitionsOf[AddOne](m.toDefinition).flatMap { i: Definition[AddOne] =>
+          aop.Select.ios(i).map(_.toTarget)
+        }
+        abs should be(
+          Seq(
+            "~AddFour|AddOne>clock".rt,
+            "~AddFour|AddOne>reset".rt,
+            "~AddFour|AddOne>in".rt,
+            "~AddFour|AddOne>out".rt,
+            "~AddFour|AddOne_1>clock".rt,
+            "~AddFour|AddOne_1>reset".rt,
+            "~AddFour|AddOne_1>in".rt,
+            "~AddFour|AddOne_1>out".rt
+          )
+        )
+
+        rel should be(
+          Seq(
+            "~AddFour|AddOne>clock".rt,
+            "~AddFour|AddOne>reset".rt,
+            "~AddFour|AddOne>in".rt,
+            "~AddFour|AddOne>out".rt,
+            "~AddFour|AddOne_1>clock".rt,
+            "~AddFour|AddOne_1>reset".rt,
+            "~AddFour|AddOne_1>in".rt,
+            "~AddFour|AddOne_1>out".rt
+          )
+        )
+
+      })
+      getFirrtlAndAnnos(new AddFour, Seq(aspect))
+    }
+    it("10.11 Select.instancesIn for typed BaseModules") {
+      val aspect = aop.inspecting.InspectingAspect({ m: HasMultipleTypeParamsInside =>
+        val targets = aop.Select.instancesIn(m.toDefinition).map { i: Instance[BaseModule] => i.toTarget }
+        targets should be(
+          Seq(
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i00:HasTypeParams".it,
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i01:HasTypeParams".it,
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i10:HasTypeParams_1".it,
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i11:HasTypeParams_1".it
+          )
+        )
+      })
+      getFirrtlAndAnnos(new HasMultipleTypeParamsInside, Seq(aspect))
+    }
+    it("10.12 Select.instancesOf for typed BaseModules if type is ignored") {
+      val aspect = aop.inspecting.InspectingAspect({ m: HasMultipleTypeParamsInside =>
+        val targets =
+          aop.Select.instancesOf[HasTypeParams[_]](m.toDefinition).map { i: Instance[HasTypeParams[_]] => i.toTarget }
+        targets should be(
+          Seq(
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i00:HasTypeParams".it,
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i01:HasTypeParams".it,
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i10:HasTypeParams_1".it,
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i11:HasTypeParams_1".it
+          )
+        )
+      })
+      getFirrtlAndAnnos(new HasMultipleTypeParamsInside, Seq(aspect))
+    }
+    it(
+      "10.13 Select.instancesOf for typed BaseModules even type is specified wrongly (should be ignored, even though we wish it weren't)"
+    ) {
+      val aspect = aop.inspecting.InspectingAspect({ m: HasMultipleTypeParamsInside =>
+        val targets = aop.Select.instancesOf[HasTypeParams[SInt]](m.toDefinition).map { i: Instance[HasTypeParams[_]] =>
+          i.toTarget
+        }
+        targets should be(
+          Seq(
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i00:HasTypeParams".it,
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i01:HasTypeParams".it,
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i10:HasTypeParams_1".it,
+            "~HasMultipleTypeParamsInside|HasMultipleTypeParamsInside/i11:HasTypeParams_1".it
+          )
+        )
+      })
+      getFirrtlAndAnnos(new HasMultipleTypeParamsInside, Seq(aspect))
+    }
   }
 }
-