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authorSchuyler Eldridge2020-06-16 11:59:15 -0400
committerSchuyler Eldridge2020-06-22 20:00:10 -0400
commit6e03f63d525aac0bdf4a59b6fe66a0b4d5a3a25a (patch)
tree482481bcfe93ea5dfcece80772ce1957fb68c74c /src/test/scala/chiselTests/experimental/GroupSpec.scala
parentcc4fa583690292d690804144fe92427f0c9f5fdf (diff)
Use ChiselStage in Tests
This migrates the tests to Chisel 3.4/FIRRTL 1.4. This primarily involves removing usages of deprecated methods including: - Remove usages of Driver - Use ChiselStage methods instead of BackendCompilationUtilities methods - Use Dependency API for custom transforms - Use extractCause to unpack StackError Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/test/scala/chiselTests/experimental/GroupSpec.scala')
-rw-r--r--src/test/scala/chiselTests/experimental/GroupSpec.scala18
1 files changed, 8 insertions, 10 deletions
diff --git a/src/test/scala/chiselTests/experimental/GroupSpec.scala b/src/test/scala/chiselTests/experimental/GroupSpec.scala
index 593179f4..f1820f5b 100644
--- a/src/test/scala/chiselTests/experimental/GroupSpec.scala
+++ b/src/test/scala/chiselTests/experimental/GroupSpec.scala
@@ -5,7 +5,7 @@ package chiselTests.experimental
import chiselTests.ChiselFlatSpec
import chisel3._
import chisel3.RawModule
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselMain}
+import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
import chisel3.util.experimental.group
import firrtl.analyses.InstanceGraph
import firrtl.options.TargetDirAnnotation
@@ -31,15 +31,13 @@ class GroupSpec extends ChiselFlatSpec {
}
def lower[T <: RawModule](gen: () => T): fir.Circuit = {
- (ChiselMain.stage.run(
- Seq(
- CompilerAnnotation(new LowFirrtlCompiler()),
- TargetDirAnnotation("test_run_dir"),
- ChiselGeneratorAnnotation(gen)
- )
- ) collectFirst {
- case firrtl.stage.FirrtlCircuitAnnotation(circuit) => circuit
- }).get
+ (new ChiselStage)
+ .execute(Array("--compiler", "low",
+ "--target-dir", "test_run_dir"),
+ Seq(ChiselGeneratorAnnotation(gen)))
+ .collectFirst {
+ case firrtl.stage.FirrtlCircuitAnnotation(circuit) => circuit
+ }.get
}
"Module Grouping" should "compile to low FIRRTL" in {