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authormergify[bot]2022-11-05 22:31:07 +0000
committerGitHub2022-11-05 22:31:07 +0000
commit017bd6b9c96974df2a3c4f35e069d60fec001f2e (patch)
tree8dab4e44284af8a0904f0817c1875a9b73243328 /src/test/scala/chiselTests/experimental/DataView.scala
parent4149157df6531d124483d992daf96cf4e62a0f0c (diff)
Support Analog in DataView (#2782) (#2828)
Co-authored-by: Megan Wachs <megan@sifive.com> (cherry picked from commit 26100a875c69bf56f7442fac82ca9c74ad3596eb) Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'src/test/scala/chiselTests/experimental/DataView.scala')
-rw-r--r--src/test/scala/chiselTests/experimental/DataView.scala12
1 files changed, 11 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/experimental/DataView.scala b/src/test/scala/chiselTests/experimental/DataView.scala
index 3673778b..cefc893c 100644
--- a/src/test/scala/chiselTests/experimental/DataView.scala
+++ b/src/test/scala/chiselTests/experimental/DataView.scala
@@ -7,7 +7,7 @@ import chisel3._
import chisel3.experimental.dataview._
import chisel3.experimental.conversions._
import chisel3.experimental.DataMirror.internal.chiselTypeClone
-import chisel3.experimental.HWTuple2
+import chisel3.experimental.{Analog, HWTuple2}
import chisel3.stage.ChiselStage
import chisel3.util.{Decoupled, DecoupledIO}
@@ -91,6 +91,16 @@ class DataViewSpec extends ChiselFlatSpec {
chirrtl should include("bar <= in")
}
+ it should "handle viewing Analogs as Analogs" in {
+ class MyModule extends Module {
+ val foo = IO(Analog(8.W))
+ val bar = IO(Analog(8.W))
+ foo <> bar.viewAs[Analog]
+ }
+ val chirrtl = ChiselStage.emitChirrtl(new MyModule)
+ chirrtl should include("attach (foo, bar)")
+ }
+
it should "handle viewing Bundles as their same concrete type" in {
class MyBundle extends Bundle {
val foo = UInt(8.W)