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authorJack Koenig2021-09-17 21:01:26 -0700
committerJack Koenig2021-09-17 21:01:26 -0700
commit5c8c19345e6711279594cf1f9ddab33623c8eba7 (patch)
treed9d6ced3934aa4a8be3dec19ddcefe50a7a93d5a /src/test/scala/chiselTests/WidthSpec.scala
parente63b9667d89768e0ec6dc8a9153335cb48a213a7 (diff)
parent958904cb2f2f65d02b2ab3ec6d9ec2e06d04e482 (diff)
Merge branch 'master' into 3.5-release
Diffstat (limited to 'src/test/scala/chiselTests/WidthSpec.scala')
-rw-r--r--src/test/scala/chiselTests/WidthSpec.scala59
1 files changed, 59 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/WidthSpec.scala b/src/test/scala/chiselTests/WidthSpec.scala
index 2a33c1d6..34159214 100644
--- a/src/test/scala/chiselTests/WidthSpec.scala
+++ b/src/test/scala/chiselTests/WidthSpec.scala
@@ -186,3 +186,62 @@ class RegInitWidthSpec extends WireDefaultRegInitSpecImpl {
def builder2[T <: Data](x: T, y: T): T = RegInit(x, y)
}
+class OpWidthSpec extends ChiselFlatSpec {
+ import firrtl._
+ import firrtl.ir._
+
+ val maxWidth = 5
+ val uIntOps: Seq[((UInt, UInt) => UInt, PrimOp)] =
+ Seq(
+ (_ +& _, PrimOps.Add),
+ (_ -& _, PrimOps.Sub),
+ (_ * _, PrimOps.Mul),
+ (_ / _, PrimOps.Div),
+ (_ % _, PrimOps.Rem),
+ (_ << _, PrimOps.Dshl),
+ (_ >> _, PrimOps.Dshr)
+ )
+
+ assertTesterPasses(new chisel3.testers.BasicTester {
+ for (i <- 0 to maxWidth) {
+ for (j <- 0 to maxWidth) {
+ for ((cOp, fOp) <- uIntOps) {
+ val args = Seq(i, j).map(w => Reference("", UIntType(IntWidth(w))))
+ fOp.propagateType(DoPrim(fOp, args, Nil, UnknownType)) match {
+ case UIntType(IntWidth(w)) =>
+ val x = 0.U(maxWidth.W).head(i)
+ val y = 0.U(maxWidth.W).head(j)
+ assert(w == cOp(x, y).getWidth)
+ }
+ }
+ }
+ }
+ stop()
+ })
+
+ val sIntOps: Seq[((SInt, SInt) => SInt, PrimOp)] =
+ Seq(
+ (_ +& _, PrimOps.Add),
+ (_ -& _, PrimOps.Sub),
+ (_ * _, PrimOps.Mul),
+ (_ / _, PrimOps.Div),
+ (_ % _, PrimOps.Rem)
+ )
+
+ assertTesterPasses(new chisel3.testers.BasicTester {
+ for (i <- 0 to maxWidth) {
+ for (j <- 0 to maxWidth) {
+ for ((cOp, fOp) <- sIntOps) {
+ val args = Seq(i, j).map(w => Reference("", SIntType(IntWidth(w))))
+ fOp.propagateType(DoPrim(fOp, args, Nil, UnknownType)) match {
+ case SIntType(IntWidth(w)) =>
+ val x = 0.U(maxWidth.W).head(i).asSInt
+ val y = 0.U(maxWidth.W).head(j).asSInt
+ assert(w == cOp(x, y).getWidth)
+ }
+ }
+ }
+ }
+ stop()
+ })
+}