Merge pull request #265 from ucb-bar/gsdt

Gsdt - Fixup to Chisel connections and direction - PR 200 revisited.

1 files changed, 3 insertions, 2 deletions

diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index 5f3d3e61..6dc2dbac 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -7,12 +7,13 @@ import org.scalatest._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
+//import chisel3.core.ExplicitCompileOptions.Strict
 
 class WhenTester() extends BasicTester {
   val cnt = Counter(4)
   when(Bool(true)) { cnt.inc() }
 
-  val out = Wire(UInt(width=3))
+  val out = Wire(UInt.width(3))
   when(cnt.value === UInt(0)) {
     out := UInt(1)
   } .elsewhen (cnt.value === UInt(1)) {
@@ -34,7 +35,7 @@ class OverlappedWhenTester() extends BasicTester {
   val cnt = Counter(4)
   when(Bool(true)) { cnt.inc() }
 
-  val out = Wire(UInt(width=3))
+  val out = Wire(UInt.width(3))
   when(cnt.value <= UInt(0)) {
     out := UInt(1)
   } .elsewhen (cnt.value <= UInt(1)) {