Merge branch 'sdtwigg_connectwrap_renamechisel3' into gsdt_tests

Revive support for firrtl flip direction.
Remove compileOptions.internalConnectionToInputOk

1 files changed, 6 insertions, 5 deletions

diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 07779faa..b8e3a154 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -19,7 +19,7 @@ import chisel3.util._
   * IMPORTANT:  The canonical way to initialize a decoupled inteface is still being debated.
   */
 class Packet extends Bundle {
-  val header = UInt(width = 1)
+  val header = UInt.width(1)
 }
 
 /**
@@ -28,8 +28,8 @@ class Packet extends Bundle {
   * The problem does not occur if the Vec is taken out
   */
 class VectorPacketIO(n: Int) extends Bundle {
-  val ins  = Vec(n, new DeqIO(new Packet()))
-  val outs = Vec(n, new EnqIO(new Packet()))
+  val ins  = Vec(n, chisel3.util.DeqIO(new Packet()))
+  val outs = Vec(n, chisel3.util.EnqIO(new Packet()))
 }
 
 /**
@@ -38,10 +38,11 @@ class VectorPacketIO(n: Int) extends Bundle {
   */
 class BrokenVectorPacketModule extends Module {
   val n  = 4
-  val io = new VectorPacketIO(n)
+  val io = IO(new VectorPacketIO(n))
 
   /* the following method of initializing the circuit may change in the future */
-  io.outs.foreach(_.init())
+  io.ins.foreach(_.nodeq())
+  io.outs.foreach(_.noenq())
 }
 
 class VectorPacketIOUnitTester extends BasicTester {