diff options
| author | Jim Lawson | 2016-12-12 09:14:33 -0800 |
|---|---|---|
| committer | GitHub | 2016-12-12 09:14:33 -0800 |
| commit | b581a24728bfba0c39ed2c032fd86f628a1e1a50 (patch) | |
| tree | f625219f936d39e760192aa69df17e776b95dd56 /src/test/scala/chiselTests/VectorPacketIO.scala | |
| parent | 0bd9ae059368570dc72f25f7939afa5cfe5fd06e (diff) | |
| parent | ad53161bbb9f67e16b88ca7a508a537f88d77e05 (diff) | |
Merge branch 'master' into buildinfousepackageaspath
Diffstat (limited to 'src/test/scala/chiselTests/VectorPacketIO.scala')
| -rw-r--r-- | src/test/scala/chiselTests/VectorPacketIO.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala index b8e3a154..bcf59e03 100644 --- a/src/test/scala/chiselTests/VectorPacketIO.scala +++ b/src/test/scala/chiselTests/VectorPacketIO.scala @@ -19,7 +19,7 @@ import chisel3.util._ * IMPORTANT: The canonical way to initialize a decoupled inteface is still being debated. */ class Packet extends Bundle { - val header = UInt.width(1) + val header = UInt(1.W) } /** |
