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authorchick2016-02-25 11:03:15 -0800
committerchick2016-02-25 11:03:15 -0800
commit2e4d7869400f121bdae692f5c5b7976b1cb58438 (patch)
tree126bc92f5be2678ec5b46e609e828ebcbfe4e573 /src/test/scala/chiselTests/VectorPacketIO.scala
parent3c0a67889280803c22fff441462d06bb5081a558 (diff)
Fixed comment punctuation and made it clearer that using an init() method for DeqIO and EnqIO initialization is likely to change.
Diffstat (limited to 'src/test/scala/chiselTests/VectorPacketIO.scala')
-rw-r--r--src/test/scala/chiselTests/VectorPacketIO.scala6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 5fff6236..99ec66a6 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -11,8 +11,11 @@ import Chisel.testers.BasicTester
* The symptom is creation of a firrtl file
* with missing declarations, the problem is exposed by
* the creation of the val outs in VectorPacketIO
+ *
* NOTE: The problem does not exist now because the initialization
* code has been removed from DeqIO and EnqIO
+ *
+ * IMPORTANT: The canonical way to initialize a decoupled inteface is still being debated.
*/
class Packet extends Bundle {
val header = UInt(width = 1)
@@ -35,6 +38,9 @@ class VectorPacketIO(n: Int) extends Bundle {
class BrokenVectorPacketModule extends Module {
val n = 4
val io = new VectorPacketIO(n)
+
+ /* the following method of initializing the circuit may change in the future */
+ io.outs.foreach(_.init())
}
class VectorPacketIOUnitTester extends BasicTester {