Add compileOptions to Module.apply, use for invalidating submod ports (#747)

Fixes #746
Also add test for https://github.com/freechipsproject/firrtl/issues/705

1 files changed, 22 insertions, 0 deletions

diff --git a/src/test/scala/chiselTests/Util.scala b/src/test/scala/chiselTests/Util.scala
new file mode 100644
index 00000000..80e37285
--- /dev/null
+++ b/src/test/scala/chiselTests/Util.scala
@@ -0,0 +1,22 @@
+// Useful utilities for tests
+
+package chiselTests
+
+import chisel3._
+import chisel3.experimental._
+
+class PassthroughModuleIO extends Bundle {
+  val in = Input(UInt(32.W))
+  val out = Output(UInt(32.W))
+}
+
+trait AbstractPassthroughModule extends RawModule {
+  val io = IO(new PassthroughModuleIO)
+  io.out := io.in
+}
+
+class PassthroughModule extends Module with AbstractPassthroughModule
+class PassthroughMultiIOModule extends MultiIOModule with AbstractPassthroughModule
+class PassthroughRawModule extends RawModule with AbstractPassthroughModule
+
+