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authorJack2022-03-15 19:37:37 +0000
committerJack2022-03-15 19:37:37 +0000
commit2f21943ff772da2171df866d4cee71dfa8127bf8 (patch)
treed00c9059c9361920036e784425641288782515d5 /src/test/scala/chiselTests/UIntOps.scala
parent1876e740a48be2e5ff5bd4fd6c2018927f1dcec2 (diff)
parentf26df23bbe0ae9b7162ed70369f24b01d75a1493 (diff)
Merge branch '3.5.x' into 3.5-release
Diffstat (limited to 'src/test/scala/chiselTests/UIntOps.scala')
-rw-r--r--src/test/scala/chiselTests/UIntOps.scala18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index 5fb86001..0010e9ac 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -199,6 +199,24 @@ class UIntOpsSpec extends ChiselPropSpec with Matchers with Utils {
a[Exception] should be thrownBy extractCause[Exception] { ChiselStage.elaborate(new BadBoolConversion) }
}
+ property("Out-of-bounds extraction from known-width UInts") {
+ a[ChiselException] should be thrownBy extractCause[ChiselException] {
+ ChiselStage.elaborate(new RawModule {
+ val u = IO(Input(UInt(2.W)))
+ u(2, 1)
+ })
+ }
+ }
+
+ property("Out-of-bounds single-bit extraction from known-width UInts") {
+ a[ChiselException] should be thrownBy extractCause[ChiselException] {
+ ChiselStage.elaborate(new RawModule {
+ val u = IO(Input(UInt(2.W)))
+ u(2)
+ })
+ }
+ }
+
property("UIntOps should elaborate") {
ChiselStage.elaborate { new UIntOps }
}