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authorSchuyler Eldridge2020-06-16 11:59:15 -0400
committerSchuyler Eldridge2020-06-22 20:00:10 -0400
commit6e03f63d525aac0bdf4a59b6fe66a0b4d5a3a25a (patch)
tree482481bcfe93ea5dfcece80772ce1957fb68c74c /src/test/scala/chiselTests/TransitNameSpec.scala
parentcc4fa583690292d690804144fe92427f0c9f5fdf (diff)
Use ChiselStage in Tests
This migrates the tests to Chisel 3.4/FIRRTL 1.4. This primarily involves removing usages of deprecated methods including: - Remove usages of Driver - Use ChiselStage methods instead of BackendCompilationUtilities methods - Use Dependency API for custom transforms - Use extractCause to unpack StackError Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/test/scala/chiselTests/TransitNameSpec.scala')
-rw-r--r--src/test/scala/chiselTests/TransitNameSpec.scala20
1 files changed, 10 insertions, 10 deletions
diff --git a/src/test/scala/chiselTests/TransitNameSpec.scala b/src/test/scala/chiselTests/TransitNameSpec.scala
index b729f244..af45988a 100644
--- a/src/test/scala/chiselTests/TransitNameSpec.scala
+++ b/src/test/scala/chiselTests/TransitNameSpec.scala
@@ -3,6 +3,7 @@ package chiselTests
import chisel3._
+import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
import chisel3.util.TransitName
import firrtl.FirrtlExecutionSuccess
@@ -38,18 +39,17 @@ class TransitNameSpec extends AnyFlatSpec with Matchers {
it should "transit a name" in {
- Driver.execute(Array("-X", "high", "--target-dir", "test_run_dir/TransitNameSpec"), () => new Top) match {
- case ChiselExecutionSuccess(_,_,Some(FirrtlExecutionSuccess(_,a))) =>
- info("""output FIRRTL includes "inst MyModule"""")
- a should include ("inst MyModule of MyModule")
+ val firrtl = (new ChiselStage)
+ .emitFirrtl(new Top, Array("--target-dir", "test_run_dir/TransitNameSpec"))
- info("""output FIRRTL includes "inst bar"""")
- a should include ("inst bar of MyModule")
+ info("""output FIRRTL includes "inst MyModule"""")
+ firrtl should include ("inst MyModule of MyModule")
- info("""output FIRRTL includes "inst baz_generated"""")
- a should include ("inst baz_generated of MyModule")
- case _ => fail
- }
+ info("""output FIRRTL includes "inst bar"""")
+ firrtl should include ("inst bar of MyModule")
+
+ info("""output FIRRTL includes "inst baz_generated"""")
+ firrtl should include ("inst baz_generated of MyModule")
}
}