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| author | chick | 2016-02-23 15:20:38 -0800 |
|---|---|---|
| committer | chick | 2016-02-23 15:20:38 -0800 |
| commit | a7af7415d6da73af418d126d72dda8ab77ceebee (patch) | |
| tree | 39d48f546293a02f79bd54234c673b4f830913eb /src/test/scala/chiselTests/TesterDriverSpec.scala | |
| parent | 7793f9fbcdeb2063961102672a36bc7ec2bda9af (diff) | |
| parent | 9bf707687777cc952287219c86e817e0f6a698ae (diff) | |
Merge branch 'master' of https://github.com/ucb-bar/chisel3
Diffstat (limited to 'src/test/scala/chiselTests/TesterDriverSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/TesterDriverSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala index dfdd07cc..3c57daae 100644 --- a/src/test/scala/chiselTests/TesterDriverSpec.scala +++ b/src/test/scala/chiselTests/TesterDriverSpec.scala @@ -22,7 +22,7 @@ class FinishTester extends BasicTester { val test_wire = Wire(UInt(1, width = test_wire_width)) // though we just set test_wire to 1, the assert below will pass because - // the finish will change it's value + // the finish will change its value assert(test_wire === UInt(test_wire_override_value)) /** In finish we use last connect semantics to alter the test_wire in the circuit |