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authorducky2016-11-17 13:01:03 -0800
committerducky2016-11-21 13:31:12 -0800
commit54d3f8dc054e55dfbd01d1aa034169a3dabe89f2 (patch)
tree7f6f9de04de6eb08878ac46be339fefc2a71395f /src/test/scala/chiselTests/TesterDriverSpec.scala
parentcd904da0aa0e96ba679906a3ee5dbdc068eace48 (diff)
Restyle a lot of test code, mainly with regex
Diffstat (limited to 'src/test/scala/chiselTests/TesterDriverSpec.scala')
-rw-r--r--src/test/scala/chiselTests/TesterDriverSpec.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index b2e811d9..c0d64a43 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -25,13 +25,13 @@ class FinishTester extends BasicTester {
// though we just set test_wire to 1, the assert below will pass because
// the finish will change its value
- assert(test_wire === UInt(test_wire_override_value))
+ assert(test_wire === test_wire_override_value.asUInt)
/** In finish we use last connect semantics to alter the test_wire in the circuit
* with a new value
*/
override def finish(): Unit = {
- test_wire := UInt(test_wire_override_value)
+ test_wire := test_wire_override_value.asUInt
}
}