diff options
| author | Richard Lin | 2016-11-21 13:44:26 -0800 |
|---|---|---|
| committer | GitHub | 2016-11-21 13:44:26 -0800 |
| commit | 3b4755716a74d4711efa3ce6799742479e17e80b (patch) | |
| tree | 56652eaa478d5dfd8cddfbe2795c0123d39d230d /src/test/scala/chiselTests/TesterDriverSpec.scala | |
| parent | cd6eb41275381a4399a8a88c886110d276bb805c (diff) | |
| parent | 81e5d00d18a5ba9ae33c10219a270148002fc672 (diff) | |
Merge pull request #372 from ucb-bar/onetrueliteral
Standardize the One True Way of specifying literals
Diffstat (limited to 'src/test/scala/chiselTests/TesterDriverSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/TesterDriverSpec.scala | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala index b2e811d9..e32368e9 100644 --- a/src/test/scala/chiselTests/TesterDriverSpec.scala +++ b/src/test/scala/chiselTests/TesterDriverSpec.scala @@ -21,17 +21,17 @@ class FinishTester extends BasicTester { stop() } - val test_wire = Wire(init=UInt(1, test_wire_width)) + val test_wire = Wire(init=1.U(test_wire_width.W)) // though we just set test_wire to 1, the assert below will pass because // the finish will change its value - assert(test_wire === UInt(test_wire_override_value)) + assert(test_wire === test_wire_override_value.asUInt) /** In finish we use last connect semantics to alter the test_wire in the circuit * with a new value */ override def finish(): Unit = { - test_wire := UInt(test_wire_override_value) + test_wire := test_wire_override_value.asUInt } } |
