diff options
| author | Henry Cook | 2015-11-04 09:21:07 -0800 |
|---|---|---|
| committer | Henry Cook | 2015-11-04 09:21:07 -0800 |
| commit | a3c9680d1e2b84693759747a4779341ba80c4a50 (patch) | |
| tree | e97ab1d8394b0463ec7f600fce7ba278bd68d93a /src/test/scala/chiselTests/Tbl.scala | |
| parent | 23d15d166d2ed32f8bd9a153a806c09982659011 (diff) | |
Remove Parameters library and refactor Driver.
In addition to removing all the extraneous Driver invocations that created various top-level Parameters instances,
this commit also lays the groundwork for stanza-firrtl/verilator based testing of Modules that extend BasicTester.
The execution-based tests have been updated accordingly. They will only succeed if firrtl and verilator binaries have been installed.
Further work is needed on individual tests to use assertions instead of .io.error.
Diffstat (limited to 'src/test/scala/chiselTests/Tbl.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Tbl.scala | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index 072f993f..40f71c69 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -23,22 +23,22 @@ class Tbl(w: Int, n: Int) extends Module { } } -class TblSpec extends ChiselPropSpec { +class TblTester(w: Int, n: Int, idxs: List[Int], values: List[Int]) extends BasicTester { + val (cnt, wrap) = Counter(Bool(true), idxs.size) + val dut = Module(new Tbl(w, n)) + val vvalues = Vec(values.map(UInt(_))) + val vidxs = Vec(idxs.map(UInt(_))) + val prev_idx = vidxs(cnt - UInt(1)) + val prev_value = vvalues(cnt - UInt(1)) + dut.io.wi := vidxs(cnt) + dut.io.ri := prev_idx + dut.io.we := Bool(true) //TODO enSequence + dut.io.d := vvalues(cnt) + when(cnt > UInt(0) && dut.io.o != prev_value) { io.done := Bool(true); io.error := prev_idx } + when(wrap) { io.done := Bool(true) } +} - class TblTester(w: Int, n: Int, idxs: List[Int], values: List[Int]) extends BasicTester { - val (cnt, wrap) = Counter(Bool(true), idxs.size) - val dut = Module(new Tbl(w, n)) - val vvalues = Vec(values.map(UInt(_))) - val vidxs = Vec(idxs.map(UInt(_))) - val prev_idx = vidxs(cnt - UInt(1)) - val prev_value = vvalues(cnt - UInt(1)) - dut.io.wi := vidxs(cnt) - dut.io.ri := prev_idx - dut.io.we := Bool(true) //TODO enSequence - dut.io.d := vvalues(cnt) - when(cnt > UInt(0) && dut.io.o != prev_value) { io.done := Bool(true); io.error := prev_idx } - when(wrap) { io.done := Bool(true) } - } +class TblSpec extends ChiselPropSpec { property("All table reads should return the previous write") { forAll(safeUIntPairN(8)) { case(w: Int, pairs: List[(Int, Int)]) => |
