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authorJack Koenig2017-11-23 06:09:59 -0800
committerGitHub2017-11-23 06:09:59 -0800
commit30e8eb552a29b22bc23faa06f5661da6129188b2 (patch)
tree790f0d895eb47945295bc410599e7c84f281d813 /src/test/scala/chiselTests/SwitchSpec.scala
parent6f58883198c083cdd79fee2e3d30f777b61dfe80 (diff)
Change switch to emit when, elsewhen, instead of when, when (#720)
Also enforce switch is conditions are mutually exclusive literals
Diffstat (limited to 'src/test/scala/chiselTests/SwitchSpec.scala')
-rw-r--r--src/test/scala/chiselTests/SwitchSpec.scala35
1 files changed, 35 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/SwitchSpec.scala b/src/test/scala/chiselTests/SwitchSpec.scala
new file mode 100644
index 00000000..2cfe16d2
--- /dev/null
+++ b/src/test/scala/chiselTests/SwitchSpec.scala
@@ -0,0 +1,35 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import chisel3._
+import chisel3.util._
+import chisel3.testers.BasicTester
+
+class SwitchSpec extends ChiselFlatSpec {
+ "switch" should "require literal conditions" in {
+ a [java.lang.IllegalArgumentException] should be thrownBy {
+ elaborate(new Module {
+ val io = IO(new Bundle {})
+ val state = RegInit(0.U)
+ val wire = WireInit(0.U)
+ switch (state) {
+ is (wire) { state := 1.U }
+ }
+ })
+ }
+ }
+ it should "require mutually exclusive conditions" in {
+ a [java.lang.IllegalArgumentException] should be thrownBy {
+ elaborate(new Module {
+ val io = IO(new Bundle {})
+ val state = RegInit(0.U)
+ switch (state) {
+ is (0.U) { state := 1.U }
+ is (1.U) { state := 2.U }
+ is (0.U) { state := 3.U }
+ }
+ })
+ }
+ }
+}