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authorJack Koenig2022-01-10 16:32:51 -0800
committerGitHub2022-01-10 16:32:51 -0800
commit2b48fd15a7711dcd44334fbbc538667a102a581a (patch)
tree4b4766347c3943d65c13e5de2d139b14821eec61 /src/test/scala/chiselTests/SwitchSpec.scala
parent92e77a97af986629766ac9038f0ebc8ab9a48fa1 (diff)
parentbff8dc0738adafa1176f6959a33ad86f6373c558 (diff)
Merge pull request #2246 from chipsalliance/scalafmt
Add scalafmt configuration and apply it.
Diffstat (limited to 'src/test/scala/chiselTests/SwitchSpec.scala')
-rw-r--r--src/test/scala/chiselTests/SwitchSpec.scala30
1 files changed, 15 insertions, 15 deletions
diff --git a/src/test/scala/chiselTests/SwitchSpec.scala b/src/test/scala/chiselTests/SwitchSpec.scala
index 12bbb9e7..52f50a53 100644
--- a/src/test/scala/chiselTests/SwitchSpec.scala
+++ b/src/test/scala/chiselTests/SwitchSpec.scala
@@ -4,30 +4,30 @@ package chiselTests
import chisel3._
import chisel3.stage.ChiselStage
-import chisel3.util.{switch, is}
+import chisel3.util.{is, switch}
class SwitchSpec extends ChiselFlatSpec with Utils {
"switch" should "require literal conditions" in {
- a [java.lang.IllegalArgumentException] should be thrownBy extractCause[IllegalArgumentException] {
+ a[java.lang.IllegalArgumentException] should be thrownBy extractCause[IllegalArgumentException] {
ChiselStage.elaborate(new Module {
val io = IO(new Bundle {})
val state = RegInit(0.U)
val wire = WireDefault(0.U)
- switch (state) {
- is (wire) { state := 1.U }
+ switch(state) {
+ is(wire) { state := 1.U }
}
})
}
}
it should "require mutually exclusive conditions" in {
- a [java.lang.IllegalArgumentException] should be thrownBy extractCause[IllegalArgumentException] {
+ a[java.lang.IllegalArgumentException] should be thrownBy extractCause[IllegalArgumentException] {
ChiselStage.elaborate(new Module {
val io = IO(new Bundle {})
val state = RegInit(0.U)
- switch (state) {
- is (0.U) { state := 1.U }
- is (1.U) { state := 2.U }
- is (0.U) { state := 3.U }
+ switch(state) {
+ is(0.U) { state := 1.U }
+ is(1.U) { state := 2.U }
+ is(0.U) { state := 3.U }
}
})
}
@@ -40,14 +40,14 @@ class SwitchSpec extends ChiselFlatSpec with Utils {
})
io.out := 0.U
- switch (io.in) {
- is (0.U) { io.out := 3.U }
- is (1.U) { io.out := 0.U }
- is (2.U) { io.out := 1.U }
- is (3.U) { io.out := 3.U }
+ switch(io.in) {
+ is(0.U) { io.out := 3.U }
+ is(1.U) { io.out := 0.U }
+ is(2.U) { io.out := 1.U }
+ is(3.U) { io.out := 3.U }
}
})
- chirrtl should not include "Conditional.scala"
+ (chirrtl should not).include("Conditional.scala")
}
}