Merge pull request #265 from ucb-bar/gsdt

Gsdt - Fixup to Chisel connections and direction - PR 200 revisited.

1 files changed, 8 insertions, 8 deletions

diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index cbd9f3e3..a72af928 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -8,15 +8,15 @@ import chisel3._
 import chisel3.util._
 
 class ChiselStack(val depth: Int) extends Module {
-  val io = new Bundle {
-    val push    = Bool(INPUT)
-    val pop     = Bool(INPUT)
-    val en      = Bool(INPUT)
-    val dataIn  = UInt(INPUT,  32)
-    val dataOut = UInt(OUTPUT, 32)
-  }
+  val io = IO(new Bundle {
+    val push    = Input(Bool())
+    val pop     = Input(Bool())
+    val en      = Input(Bool())
+    val dataIn  = Input(UInt.width(32))
+    val dataOut = Output(UInt.width(32))
+  })
 
-  val stack_mem = Mem(depth, UInt(width = 32))
+  val stack_mem = Mem(depth, UInt.width(32))
   val sp        = Reg(init = UInt(0, width = log2Up(depth + 1)))
   val out       = Reg(init = UInt(0, width = 32))