summaryrefslogtreecommitdiff
path: root/src/test/scala/chiselTests/Stack.scala
diff options
context:
space:
mode:
authorducky2016-11-17 13:16:40 -0800
committerducky2016-11-21 13:31:12 -0800
commit37a569372c70a651c813d0beb44124878a596e73 (patch)
treec5a691564f37110e1c056227a9d0818ea337af69 /src/test/scala/chiselTests/Stack.scala
parent73906fcc796b259c81d5df7733968b77fbb81ba8 (diff)
Fix all deprecations from new style
Diffstat (limited to 'src/test/scala/chiselTests/Stack.scala')
-rw-r--r--src/test/scala/chiselTests/Stack.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index ce8fd9fc..58a05937 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -17,7 +17,7 @@ class ChiselStack(val depth: Int) extends Module {
})
val stack_mem = Mem(depth, UInt(32.W))
- val sp = Reg(init = UInt(0, width = log2Up(depth + 1)))
+ val sp = Reg(init = 0.U(log2Up(depth+1).W))
val out = Reg(init = 0.U(32.W))
when (io.en) {