diff options
| author | Jack Koenig | 2022-01-10 10:39:52 -0800 |
|---|---|---|
| committer | Jack Koenig | 2022-01-10 15:53:55 -0800 |
| commit | 3131c0daad41dea78bede4517669e376c41a325a (patch) | |
| tree | 55baed78a6a01f80ff3952a08233ca553a19964f /src/test/scala/chiselTests/Stack.scala | |
| parent | dd36f97a82746cec0b25b94651581fe799e24579 (diff) | |
Apply scalafmt
Command:
sbt scalafmtAll
Diffstat (limited to 'src/test/scala/chiselTests/Stack.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Stack.scala | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index cb21e2c0..085f4e34 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -8,25 +8,25 @@ import chisel3.util._ class ChiselStack(val depth: Int) extends Module { val io = IO(new Bundle { - val push = Input(Bool()) - val pop = Input(Bool()) - val en = Input(Bool()) - val dataIn = Input(UInt(32.W)) + val push = Input(Bool()) + val pop = Input(Bool()) + val en = Input(Bool()) + val dataIn = Input(UInt(32.W)) val dataOut = Output(UInt(32.W)) }) val stack_mem = Mem(depth, UInt(32.W)) - val sp = RegInit(0.U(log2Ceil(depth + 1).W)) - val out = RegInit(0.U(32.W)) + val sp = RegInit(0.U(log2Ceil(depth + 1).W)) + val out = RegInit(0.U(32.W)) - when (io.en) { + when(io.en) { when(io.push && (sp < depth.asUInt)) { stack_mem(sp) := io.dataIn sp := sp +% 1.U - } .elsewhen(io.pop && (sp > 0.U)) { + }.elsewhen(io.pop && (sp > 0.U)) { sp := sp -% 1.U } - when (sp > 0.U) { + when(sp > 0.U) { out := stack_mem(sp -% 1.U) } } @@ -65,7 +65,7 @@ class StackTester(c: Stack) extends Tester(c) { expect(c.io.dataOut, dataOut) } } -*/ + */ class StackSpec extends ChiselPropSpec { @@ -73,5 +73,5 @@ class StackSpec extends ChiselPropSpec { ChiselStage.elaborate { new ChiselStack(2) } } - ignore("StackTester should return the correct result") { } + ignore("StackTester should return the correct result") {} } |
