diff options
| author | ducky | 2016-11-17 13:06:57 -0800 |
|---|---|---|
| committer | ducky | 2016-11-21 13:31:12 -0800 |
| commit | 73906fcc796b259c81d5df7733968b77fbb81ba8 (patch) | |
| tree | 5f85e2e3cbf4753ddb4e8fa1014c465fa7005555 /src/test/scala/chiselTests/Risc.scala | |
| parent | 54d3f8dc054e55dfbd01d1aa034169a3dabe89f2 (diff) | |
All remaining automatable regex re-styles
Diffstat (limited to 'src/test/scala/chiselTests/Risc.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Risc.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala index ae99df59..744e3631 100644 --- a/src/test/scala/chiselTests/Risc.scala +++ b/src/test/scala/chiselTests/Risc.scala @@ -73,7 +73,7 @@ class RiscTester(c: Risc) extends Tester(c) { step(1) } def I (op: UInt, rc: Int, ra: Int, rb: Int) = { - // val cr = Cat(op, UInt(rc, 8), UInt(ra, 8), UInt(rb, 8)).litValue() + // val cr = Cat(op, rc.asUInt(8.W), ra.asUInt(8.W), rb.asUInt(8.W)).litValue() val cr = op.litValue() << 24 | rc << 16 | ra << 8 | rb println("I = " + cr) // scalastyle:ignore regex cr |