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| author | Jim Lawson | 2016-04-26 13:37:39 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-04-26 13:37:39 -0700 |
| commit | 6183533596a1706c65cb20d07a9d42eadac32df2 (patch) | |
| tree | 18a215bf0b19b50d8de8cbaa815f9918d4c7b0b8 /src/test/scala/chiselTests/Risc.scala | |
| parent | 09958f63470697188e1ed1a01c7ea39b8c56e7ef (diff) | |
Replace deprecated usage in tests. Issue #149
Diffstat (limited to 'src/test/scala/chiselTests/Risc.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Risc.scala | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala index ad5cf762..3daa5bd2 100644 --- a/src/test/scala/chiselTests/Risc.scala +++ b/src/test/scala/chiselTests/Risc.scala @@ -12,8 +12,9 @@ class Risc extends Module { val valid = Bool(OUTPUT) val out = Bits(OUTPUT, 32) } - val file = Mem(Bits(width = 32), 256) - val code = Mem(Bits(width = 32), 256) + val memSize = 256 + val file = Mem(memSize, Bits(width = 32)) + val code = Mem(memSize, Bits(width = 32)) val pc = Reg(init=UInt(0, 8)) val add_op :: imm_op :: Nil = Enum(Bits(width = 8), 2) |