Merge pull request #1519 from freechipsproject/no-scalastyle

Remove scalastyle configurations

1 files changed, 2 insertions, 4 deletions

diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index de39e723..765e1e56 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -55,7 +55,6 @@ class Risc extends Module {
   }
 }
 
-// scalastyle:off regex
 /*
 class RiscTester(c: Risc) extends Tester(c) {
   def wr(addr: BigInt, data: BigInt)  = {
@@ -77,7 +76,7 @@ class RiscTester(c: Risc) extends Tester(c) {
   def I (op: UInt, rc: Int, ra: Int, rb: Int) = {
     // val cr = Cat(op, rc.asUInt(8.W), ra.asUInt(8.W), rb.asUInt(8.W)).litValue()
     val cr = op.litValue() << 24 | rc << 16 | ra << 8 | rb
-    println("I = " + cr)    // scalastyle:ignore regex
+    println("I = " + cr)
     cr
   }
 
@@ -89,7 +88,7 @@ class RiscTester(c: Risc) extends Tester(c) {
   for (addr <- 0 until app.length)
     wr(addr, app(addr))
   def dump(k: Int) {
-    println("K = " + k)  // scalastyle:ignore regex
+    println("K = " + k)
     peek(c.ra)
     peek(c.rb)
     peek(c.rc)
@@ -113,7 +112,6 @@ class RiscTester(c: Risc) extends Tester(c) {
   expect(c.io.out, 4)
 }
 */
-// scalastyle:on regex
 
 class RiscSpec extends ChiselPropSpec {