Merge pull request #2246 from chipsalliance/scalafmt

Add scalafmt configuration and apply it.

1 files changed, 18 insertions, 18 deletions

diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 74c55a12..e0eacb90 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -8,47 +8,47 @@ import chisel3.util._
 
 class Risc extends Module {
   val io = IO(new Bundle {
-    val isWr   = Input(Bool())
+    val isWr = Input(Bool())
     val wrAddr = Input(UInt(8.W))
     val wrData = Input(Bits(32.W))
-    val boot   = Input(Bool())
-    val valid  = Output(Bool())
-    val out    = Output(Bits(32.W))
+    val boot = Input(Bool())
+    val valid = Output(Bool())
+    val out = Output(Bits(32.W))
   })
   val memSize = 256
   val file = Mem(memSize, Bits(32.W))
   val code = Mem(memSize, Bits(32.W))
-  val pc   = RegInit(0.U(8.W))
+  val pc = RegInit(0.U(8.W))
 
   val add_op :: imm_op :: Nil = Enum(2)
 
   val inst = code(pc)
-  val op   = inst(31,24)
-  val rci  = inst(23,16)
-  val rai  = inst(15, 8)
-  val rbi  = inst( 7, 0)
+  val op = inst(31, 24)
+  val rci = inst(23, 16)
+  val rai = inst(15, 8)
+  val rbi = inst(7, 0)
 
   val ra = Mux(rai === 0.U, 0.U, file(rai))
   val rb = Mux(rbi === 0.U, 0.U, file(rbi))
   val rc = Wire(Bits(32.W))
 
   io.valid := false.B
-  io.out   := 0.U
-  rc       := 0.U
+  io.out := 0.U
+  rc := 0.U
 
-  when (io.isWr) {
+  when(io.isWr) {
     code(io.wrAddr) := io.wrData
-  } .elsewhen (io.boot) {
+  }.elsewhen(io.boot) {
     pc := 0.U
-  } .otherwise {
+  }.otherwise {
     switch(op) {
       is(add_op) { rc := ra +% rb }
       is(imm_op) { rc := (rai << 8) | rbi }
     }
     io.out := rc
-    when (rci === 255.U) {
+    when(rci === 255.U) {
       io.valid := true.B
-    } .otherwise {
+    }.otherwise {
       file(rci) := rc
     }
     pc := pc +% 1.U
@@ -111,7 +111,7 @@ class RiscTester(c: Risc) extends Tester(c) {
   expect(k <= 10, "TIME LIMIT")
   expect(c.io.out, 4)
 }
-*/
+ */
 
 class RiscSpec extends ChiselPropSpec {
 
@@ -119,5 +119,5 @@ class RiscSpec extends ChiselPropSpec {
     ChiselStage.elaborate { new Risc }
   }
 
-  ignore("RiscTester should return the correct result") { }
+  ignore("RiscTester should return the correct result") {}
 }