summaryrefslogtreecommitdiff
path: root/src/test/scala/chiselTests/ResetSpec.scala
diff options
context:
space:
mode:
authorSchuyler Eldridge2020-06-22 20:34:46 -0400
committerGitHub2020-06-22 20:34:46 -0400
commit9f44b593efe4830aeb56d17f5ed59277a74832f8 (patch)
treeac43010dd7fc2a14303497f95e12f2a40bb16d0e /src/test/scala/chiselTests/ResetSpec.scala
parentd099d01ae6b11d8befdf7b32ab74c3167a552984 (diff)
parentb5e59895e13550006fd8e951b7e9483de00f82dd (diff)
Merge pull request #1481 from freechipsproject/driver-deprecations
Remove Deprecated Usages of chisel3.Driver, CircuitForm
Diffstat (limited to 'src/test/scala/chiselTests/ResetSpec.scala')
-rw-r--r--src/test/scala/chiselTests/ResetSpec.scala13
1 files changed, 7 insertions, 6 deletions
diff --git a/src/test/scala/chiselTests/ResetSpec.scala b/src/test/scala/chiselTests/ResetSpec.scala
index d08be8fa..9d67637d 100644
--- a/src/test/scala/chiselTests/ResetSpec.scala
+++ b/src/test/scala/chiselTests/ResetSpec.scala
@@ -3,6 +3,7 @@
package chiselTests
import chisel3._
+import chisel3.stage.ChiselStage
import chisel3.util.{Counter, Queue}
import chisel3.testers.BasicTester
@@ -35,12 +36,12 @@ class AbstractResetDontCareModule extends RawModule {
}
-class ResetSpec extends ChiselFlatSpec {
+class ResetSpec extends ChiselFlatSpec with Utils {
behavior of "Reset"
it should "be able to be connected to DontCare" in {
- elaborate(new AbstractResetDontCareModule)
+ ChiselStage.elaborate(new AbstractResetDontCareModule)
}
it should "allow writing modules that are reset agnostic" in {
@@ -72,22 +73,22 @@ class ResetSpec extends ChiselFlatSpec {
behavior of "Users"
they should "be able to force implicit reset to be synchronous" in {
- val fir = generateFirrtl(new MultiIOModule with RequireSyncReset {
+ val fir = (new ChiselStage).emitChirrtl(new MultiIOModule with RequireSyncReset {
reset shouldBe a [Bool]
})
fir should include ("input reset : UInt<1>")
}
they should "be able to force implicit reset to be asynchronous" in {
- val fir = generateFirrtl(new MultiIOModule with RequireAsyncReset {
+ val fir = (new ChiselStage).emitChirrtl(new MultiIOModule with RequireAsyncReset {
reset shouldBe an [AsyncReset]
})
fir should include ("input reset : AsyncReset")
}
"Chisel" should "error if sync and async modules are nested" in {
- a [ChiselException] shouldBe thrownBy {
- elaborate(new MultiIOModule with RequireAsyncReset {
+ a [ChiselException] should be thrownBy extractCause[ChiselException] {
+ ChiselStage.elaborate(new MultiIOModule with RequireAsyncReset {
val mod = Module(new MultiIOModule with RequireSyncReset)
})
}