Add support for asynchronous reset (#1011)

Adds new AsyncReset and "abstract" Reset types. Reset is inferred
in FIRRTL to be either AsyncReset or Bool. The "reset type" of a
register is set by the type of its reset signal:

  val asyncReset: AsyncReset = IO(Input(AsyncReset()))
  val syncReset: Bool = IO(Input(Bool()))
  val abstractReset: Reset = IO(Input(Reset()))

  val asyncReg = withReset(asyncReset) { RegInit(0.U) }
  val syncReg = withReset(syncReset) { RegInit(0.U) }
  val inferredReg = withReset(abstractReset) { RegInit(0.U) }

AsyncReset can be cast to and from Bool. Whereas synchronous reset is
equivalent to a mux in front of a flip-flop and thus can be driven by
logic, asynchronous reset requires that the reset value is a constant.
This is checked in FIRRTL.

Inference of the concrete type of a Reset occurs based on the type the
Reset's drivers. This inference is very simple, it is simple forward propagation
of the type, but it allows for writing blocks and modules that are agnostic
to the reset type. In particular, the implicit `reset` value in MultiIOModule
and thus Module is now concretely an instance of Reset and thus will be
inferred in FIRRTL.

1 files changed, 50 insertions, 0 deletions

diff --git a/src/test/scala/chiselTests/ResetSpec.scala b/src/test/scala/chiselTests/ResetSpec.scala
new file mode 100644
index 00000000..297c5516
--- /dev/null
+++ b/src/test/scala/chiselTests/ResetSpec.scala
@@ -0,0 +1,50 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import chisel3._
+import chisel3.experimental.{IO, RawModule}
+import chisel3.util.{Counter, Queue}
+import chisel3.testers.BasicTester
+
+class ResetAgnosticModule extends RawModule {
+  val clk = IO(Input(Clock()))
+  val rst = IO(Input(Reset()))
+  val out = IO(Output(UInt(8.W)))
+
+  val reg = withClockAndReset(clk, rst)(RegInit(0.U(8.W)))
+  reg := reg + 1.U
+  out := reg
+}
+
+
+class ResetSpec extends ChiselFlatSpec {
+
+  behavior of "Reset"
+
+  it should "allow writing modules that are reset agnostic" in {
+    val sync = compile(new Module {
+      val io = IO(new Bundle {
+        val out = Output(UInt(8.W))
+      })
+      val inst = Module(new ResetAgnosticModule)
+      inst.clk := clock
+      inst.rst := reset
+      assert(inst.rst.isInstanceOf[chisel3.ResetType])
+      io.out := inst.out
+    })
+    sync should include ("always @(posedge clk)")
+
+    val async = compile(new Module {
+      val io = IO(new Bundle {
+        val out = Output(UInt(8.W))
+      })
+      val inst = Module(new ResetAgnosticModule)
+      inst.clk := clock
+      inst.rst := reset.asTypeOf(AsyncReset())
+      assert(inst.rst.isInstanceOf[chisel3.ResetType])
+      io.out := inst.out
+    })
+    async should include ("always @(posedge clk or posedge rst)")
+  }
+}