diff options
| author | Schuyler Eldridge | 2019-05-07 02:21:50 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-05-09 12:47:32 -0400 |
| commit | aaee64deb9c4990d0e38043a2b6a4ce747bb6935 (patch) | |
| tree | 5ce84e585188bf1a934f6b404dc26e1d4175b83d /src/test/scala/chiselTests/QueueSpec.scala | |
| parent | f35f2a2784d8df7c079ee46eb33eeffd805edb44 (diff) | |
Deprecate LFSR16, use FibonacciLFSR internally
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/test/scala/chiselTests/QueueSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/QueueSpec.scala | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/test/scala/chiselTests/QueueSpec.scala b/src/test/scala/chiselTests/QueueSpec.scala index 3f723ecf..994f3e6d 100644 --- a/src/test/scala/chiselTests/QueueSpec.scala +++ b/src/test/scala/chiselTests/QueueSpec.scala @@ -9,6 +9,7 @@ import org.scalacheck._ import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ +import chisel3.util.random.LFSR class ThingsPassThroughTester(elements: Seq[Int], queueDepth: Int, bitWidth: Int, tap: Int) extends BasicTester { val q = Module(new Queue(UInt(bitWidth.W), queueDepth)) @@ -19,7 +20,7 @@ class ThingsPassThroughTester(elements: Seq[Int], queueDepth: Int, bitWidth: Int val outCnt = Counter(elements.length + 1) q.io.enq.valid := (inCnt.value < elements.length.U) - q.io.deq.ready := LFSR16()(tap) + q.io.deq.ready := LFSR(16)(tap) q.io.enq.bits := elems(inCnt.value) when(q.io.enq.fire()) { @@ -47,7 +48,7 @@ class QueueReasonableReadyValid(elements: Seq[Int], queueDepth: Int, bitWidth: I //Queue should be full or ready assert(q.io.enq.ready || q.io.count === queueDepth.U) - q.io.deq.ready := LFSR16()(tap) + q.io.deq.ready := LFSR(16)(tap) //Queue should be empty or valid assert(q.io.deq.valid || q.io.count === 0.U) @@ -72,7 +73,7 @@ class CountIsCorrectTester(elements: Seq[Int], queueDepth: Int, bitWidth: Int, t val outCnt = Counter(elements.length + 1) q.io.enq.valid := (inCnt.value < elements.length.U) - q.io.deq.ready := LFSR16()(tap) + q.io.deq.ready := LFSR(16)(tap) q.io.enq.bits := elems(inCnt.value) when(q.io.enq.fire()) { @@ -99,7 +100,7 @@ class QueueSinglePipeTester(elements: Seq[Int], bitWidth: Int, tap: Int) extends val outCnt = Counter(elements.length + 1) q.io.enq.valid := (inCnt.value < elements.length.U) - q.io.deq.ready := LFSR16()(tap) + q.io.deq.ready := LFSR(16)(tap) assert(q.io.enq.ready || (q.io.count === 1.U && !q.io.deq.ready)) @@ -125,7 +126,7 @@ class QueuePipeTester(elements: Seq[Int], queueDepth: Int, bitWidth: Int, tap: I val outCnt = Counter(elements.length + 1) q.io.enq.valid := (inCnt.value < elements.length.U) - q.io.deq.ready := LFSR16()(tap) + q.io.deq.ready := LFSR(16)(tap) assert(q.io.enq.ready || (q.io.count === queueDepth.U && !q.io.deq.ready)) @@ -154,7 +155,7 @@ class QueueFlowTester(elements: Seq[Int], queueDepth: Int, bitWidth: Int, tap: I //Queue should be full or ready assert(q.io.enq.ready || q.io.count === queueDepth.U) - q.io.deq.ready := LFSR16()(tap) + q.io.deq.ready := LFSR(16)(tap) //Queue should be empty or valid assert(q.io.deq.valid || (q.io.count === 0.U && !q.io.enq.fire())) |