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| author | Andrew Waterman | 2016-01-23 21:11:09 -0800 |
|---|---|---|
| committer | Andrew Waterman | 2016-01-23 21:11:09 -0800 |
| commit | 86a6c6bcdc349f40dcc31bce1931dc7c427da674 (patch) | |
| tree | 37fe805a7eea16e2ae6bdb1d6a516974cfaae89a /src/test/scala/chiselTests/ParameterizedModule.scala | |
| parent | b4517e0fb563271464bd40ddf9a46a40fd827da4 (diff) | |
Change implicit clock name to clk to match Chisel2
This allows us to share Verilog test harnesses between the two.
Diffstat (limited to 'src/test/scala/chiselTests/ParameterizedModule.scala')
0 files changed, 0 insertions, 0 deletions