Merge pull request #265 from ucb-bar/gsdt

Gsdt - Fixup to Chisel connections and direction - PR 200 revisited.

1 files changed, 5 insertions, 5 deletions

diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
index 3fb0f955..42df6802 100644
--- a/src/test/scala/chiselTests/Padding.scala
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -5,11 +5,11 @@ package chiselTests
 import chisel3._
 
 class Padder extends Module {
-  val io = new Bundle {
-    val a   = Bits(INPUT,  4)
-    val asp = SInt(OUTPUT, 8)
-    val aup = UInt(OUTPUT, 8)
-  }
+  val io = IO(new Bundle {
+    val a   = Input(UInt.width(4))
+    val asp = Output(SInt.width(8))
+    val aup = Output(UInt.width(8))
+  })
   io.asp := io.a.asSInt
   io.aup := io.a.asUInt
 }