diff options
| author | Jim Lawson | 2016-12-02 12:51:03 -0800 |
|---|---|---|
| committer | GitHub | 2016-12-02 12:51:03 -0800 |
| commit | d3ec37edd39799e8cf039e5caed915c00dff7eeb (patch) | |
| tree | 03329ddc11ca15b9d6c7f832354a9cba20c87843 /src/test/scala/chiselTests/Padding.scala | |
| parent | 1b53d893816d349f5ea18fa0ed13325b9f1b6917 (diff) | |
| parent | eba224e524b249207b47a3b378458c61c9b66e2c (diff) | |
Merge branch 'master' into exceptionfix
Diffstat (limited to 'src/test/scala/chiselTests/Padding.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Padding.scala | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala index 42df6802..6f256b64 100644 --- a/src/test/scala/chiselTests/Padding.scala +++ b/src/test/scala/chiselTests/Padding.scala @@ -6,9 +6,9 @@ import chisel3._ class Padder extends Module { val io = IO(new Bundle { - val a = Input(UInt.width(4)) - val asp = Output(SInt.width(8)) - val aup = Output(UInt.width(8)) + val a = Input(UInt(4.W)) + val asp = Output(SInt(8.W)) + val aup = Output(UInt(8.W)) }) io.asp := io.a.asSInt io.aup := io.a.asUInt |
