diff options
| author | Richard Lin | 2016-11-21 13:44:26 -0800 |
|---|---|---|
| committer | GitHub | 2016-11-21 13:44:26 -0800 |
| commit | 3b4755716a74d4711efa3ce6799742479e17e80b (patch) | |
| tree | 56652eaa478d5dfd8cddfbe2795c0123d39d230d /src/test/scala/chiselTests/Padding.scala | |
| parent | cd6eb41275381a4399a8a88c886110d276bb805c (diff) | |
| parent | 81e5d00d18a5ba9ae33c10219a270148002fc672 (diff) | |
Merge pull request #372 from ucb-bar/onetrueliteral
Standardize the One True Way of specifying literals
Diffstat (limited to 'src/test/scala/chiselTests/Padding.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Padding.scala | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala index 42df6802..6f256b64 100644 --- a/src/test/scala/chiselTests/Padding.scala +++ b/src/test/scala/chiselTests/Padding.scala @@ -6,9 +6,9 @@ import chisel3._ class Padder extends Module { val io = IO(new Bundle { - val a = Input(UInt.width(4)) - val asp = Output(SInt.width(8)) - val aup = Output(UInt.width(8)) + val a = Input(UInt(4.W)) + val asp = Output(SInt(8.W)) + val aup = Output(UInt(8.W)) }) io.asp := io.a.asSInt io.aup := io.a.asUInt |
