summaryrefslogtreecommitdiff
path: root/src/test/scala/chiselTests/NamingAnnotationTest.scala
diff options
context:
space:
mode:
authorJack Koenig2021-01-21 22:50:12 -0800
committerGitHub2021-01-21 22:50:12 -0800
commitdd6871b8b3f2619178c2a333d9d6083805d99e16 (patch)
tree825776855e7d2fc28ef32ebb05df7339c24e00b3 /src/test/scala/chiselTests/NamingAnnotationTest.scala
parent616256c35cb7de8fcd97df56af1986b747abe54d (diff)
parent53c24cb0a369d4c4f57c28c098b30e4d3640eac2 (diff)
Merge pull request #1745 from chipsalliance/remove-val-io
Remove "val io" and rename MultiIOModule to Module
Diffstat (limited to 'src/test/scala/chiselTests/NamingAnnotationTest.scala')
-rw-r--r--src/test/scala/chiselTests/NamingAnnotationTest.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/NamingAnnotationTest.scala b/src/test/scala/chiselTests/NamingAnnotationTest.scala
index 43ec837d..2226a48a 100644
--- a/src/test/scala/chiselTests/NamingAnnotationTest.scala
+++ b/src/test/scala/chiselTests/NamingAnnotationTest.scala
@@ -9,7 +9,7 @@ import chisel3.stage.ChiselStage
import scala.collection.mutable.ListBuffer
-trait NamedModuleTester extends MultiIOModule {
+trait NamedModuleTester extends Module {
val expectedNameMap = ListBuffer[(InstanceId, String)]()
val expectedModuleNameMap = ListBuffer[(Module, String)]()