Programmatic Port Creation (#833)

Add chisel3.experimental.IO for programmatic port creation in Raw and
MultiIOModules. suggestName is required to name ports that cannot be
named by reflection. Two ports cannot be given the same name.

1 files changed, 2 insertions, 4 deletions

diff --git a/src/test/scala/chiselTests/NamingAnnotationTest.scala b/src/test/scala/chiselTests/NamingAnnotationTest.scala
index a7b9b75c..07962aaf 100644
--- a/src/test/scala/chiselTests/NamingAnnotationTest.scala
+++ b/src/test/scala/chiselTests/NamingAnnotationTest.scala
@@ -4,16 +4,14 @@ package chiselTests
 
 import chisel3._
 import chisel3.internal.InstanceId
-import chisel3.experimental.{chiselName, dump}
+import chisel3.experimental.{chiselName, dump, MultiIOModule}
 import org.scalatest._
 import org.scalatest.prop._
 import chisel3.testers.BasicTester
 
 import scala.collection.mutable.ListBuffer
 
-trait NamedModuleTester extends Module {
-  val io = IO(new Bundle() {})  // Named module testers don't need IO
-
+trait NamedModuleTester extends MultiIOModule {
   val expectedNameMap = ListBuffer[(InstanceId, String)]()
   val expectedModuleNameMap = ListBuffer[(Module, String)]()