Apply scalafmt

Command:
sbt scalafmtAll

1 files changed, 10 insertions, 9 deletions

diff --git a/src/test/scala/chiselTests/MuxSpec.scala b/src/test/scala/chiselTests/MuxSpec.scala
index 33024f0b..03505f2d 100644
--- a/src/test/scala/chiselTests/MuxSpec.scala
+++ b/src/test/scala/chiselTests/MuxSpec.scala
@@ -4,21 +4,21 @@ package chiselTests
 
 import chisel3._
 import chisel3.stage.ChiselStage
-import chisel3.util.{MuxLookup, log2Ceil}
+import chisel3.util.{log2Ceil, MuxLookup}
 import chisel3.testers.BasicTester
 
 class MuxTester extends BasicTester {
   assert(Mux(0.B, 1.U, 2.U) === 2.U)
   assert(Mux(1.B, 1.U, 2.U) === 1.U)
   val dontCareMux1 = Wire(UInt())
-  dontCareMux1 := Mux(0.B, DontCare, 4.U)  // note: Mux output of type Element
+  dontCareMux1 := Mux(0.B, DontCare, 4.U) // note: Mux output of type Element
   assert(dontCareMux1 === 4.U)
 
   val dontCareMux2 = Wire(UInt())
-  dontCareMux2 := Mux(1.B, 3.U, DontCare)  // note: Mux output of type Element
+  dontCareMux2 := Mux(1.B, 3.U, DontCare) // note: Mux output of type Element
   assert(dontCareMux2 === 3.U)
 
-  Mux(0.B, 3.U, DontCare)  // just to make sure nothing crashes, any result is valid
+  Mux(0.B, 3.U, DontCare) // just to make sure nothing crashes, any result is valid
   stop()
 }
 
@@ -45,27 +45,28 @@ class MuxLookupExhaustiveSpec extends ChiselPropSpec {
 
   val incomplete = () => Seq(0.U -> 1.U, 1.U -> 2.U, 2.U -> 3.U)
   property("The default value should not be optimized away for an incomplete MuxLookup") {
-    ChiselStage.emitChirrtl(new MuxLookupWrapper(keyWidth, default, incomplete)) should include (firrtlLit)
+    ChiselStage.emitChirrtl(new MuxLookupWrapper(keyWidth, default, incomplete)) should include(firrtlLit)
   }
 
   val exhaustive = () => (3.U -> 0.U) +: incomplete()
   property("The default value should be optimized away for an exhaustive MuxLookup") {
-    ChiselStage.emitChirrtl(new MuxLookupWrapper(keyWidth, default, exhaustive)) should not include (firrtlLit)
+    (ChiselStage.emitChirrtl(new MuxLookupWrapper(keyWidth, default, exhaustive)) should not).include(firrtlLit)
   }
 
   val overlap = () => (4096.U -> 0.U) +: incomplete()
   property("The default value should not be optimized away for a MuxLookup with 2^{keyWidth} non-distinct mappings") {
-    ChiselStage.emitChirrtl(new MuxLookupWrapper(keyWidth, default, overlap)) should include (firrtlLit)
+    ChiselStage.emitChirrtl(new MuxLookupWrapper(keyWidth, default, overlap)) should include(firrtlLit)
   }
 
   val nonLiteral = () => { val foo = Wire(UInt()); (foo -> 1.U) +: incomplete() }
   property("The default value should not be optimized away for a MuxLookup with a non-literal") {
-    ChiselStage.emitChirrtl(new MuxLookupWrapper(keyWidth, default, nonLiteral)) should include (firrtlLit)
+    ChiselStage.emitChirrtl(new MuxLookupWrapper(keyWidth, default, nonLiteral)) should include(firrtlLit)
   }
 
   val nonLiteralStillFull = () => { val foo = Wire(UInt()); (foo -> 1.U) +: exhaustive() }
   property("The default value should be optimized away for a MuxLookup with a non-literal that is still full") {
-    ChiselStage.emitChirrtl(new MuxLookupWrapper(keyWidth, default, nonLiteralStillFull)) should not include (firrtlLit)
+    (ChiselStage.emitChirrtl(new MuxLookupWrapper(keyWidth, default, nonLiteralStillFull)) should not)
+      .include(firrtlLit)
   }
 
 }