Merge pull request #2246 from chipsalliance/scalafmt

Add scalafmt configuration and apply it.

1 files changed, 2 insertions, 3 deletions

diff --git a/src/test/scala/chiselTests/MultiIOModule.scala b/src/test/scala/chiselTests/MultiIOModule.scala
index 9abf324b..c65d8fc4 100644
--- a/src/test/scala/chiselTests/MultiIOModule.scala
+++ b/src/test/scala/chiselTests/MultiIOModule.scala
@@ -6,7 +6,7 @@ import chisel3._
 import chisel3.testers.BasicTester
 
 class MultiIOPlusOne extends Module {
-  val in  = IO(Input(UInt(32.W)))
+  val in = IO(Input(UInt(32.W)))
   val out = IO(Output(UInt(32.W)))
 
   out := in + 1.asUInt
@@ -33,8 +33,7 @@ trait MultiIOTrait extends Module {
 
 // Composition of the two above traits, example of IO composition directly using multiple top-level
 // IOs rather than indirectly by constraining the type of the single .io field.
-class ComposedMultiIOModule extends Module
-    with LiteralOutputTrait with MultiIOTrait {
+class ComposedMultiIOModule extends Module with LiteralOutputTrait with MultiIOTrait {
   val topModuleIO = IO(Input(UInt(32.W)))
   myTraitIO := topModuleIO
 }