Merge branch '3.5.x' into 3.5-release

1 files changed, 0 insertions, 8 deletions

diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala
index 381b4009..29ec6509 100644
--- a/src/test/scala/chiselTests/MultiClockSpec.scala
+++ b/src/test/scala/chiselTests/MultiClockSpec.scala
@@ -166,14 +166,6 @@ class MultiClockSpec extends ChiselFlatSpec with Utils {
   }
 
   "Differing clocks at memory and read accessor instantiation" should "warn" in {
-    class modMemReadDifferingClock extends Module {
-      val myClock = IO(Input(Clock()))
-      val mem = withClock(myClock) { Mem(4, UInt(8.W)) }
-      val readVal = mem.read(0.U)
-    }
-    val (logMemReadDifferingClock, _) = grabLog(ChiselStage.elaborate(new modMemReadDifferingClock))
-    logMemReadDifferingClock should include("memory is different")
-
     class modSyncReadMemReadDifferingClock extends Module {
       val myClock = IO(Input(Clock()))
       val mem = withClock(myClock) { SyncReadMem(4, UInt(8.W)) }