diff options
| author | Jack Koenig | 2018-06-01 12:16:11 -0700 |
|---|---|---|
| committer | GitHub | 2018-06-01 12:16:11 -0700 |
| commit | d0cdd3b4c3713bb7454868fac7fa9c43bae2332c (patch) | |
| tree | 1b0ec2359ae56b3f2be006a09eca50a6b430ede4 /src/test/scala/chiselTests/MultiClockSpec.scala | |
| parent | 7df245e7c01d28de51d8dc27a35756e7f5eb4331 (diff) | |
Literals set their ref so they no longer get named (#826)
Fixes #763
Add tests for #763 and #472
This has a few implications
* Constructing a literal no longer increments _T_ suffixes
* Internally, wrapping a literal Bits in Node(...) will work
* Literal Bools work in withReset/withClockAndReset
Diffstat (limited to 'src/test/scala/chiselTests/MultiClockSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/MultiClockSpec.scala | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala index 7886649f..778806e3 100644 --- a/src/test/scala/chiselTests/MultiClockSpec.scala +++ b/src/test/scala/chiselTests/MultiClockSpec.scala @@ -142,6 +142,18 @@ class MultiClockSpec extends ChiselFlatSpec { assert(withReset(this.reset) { 5 } == 5) }) } + it should "support literal Bools" in { + assertTesterPasses(new BasicTester { + val reg = withReset(true.B) { + RegInit(6.U) + } + reg := reg - 1.U + // The reg is always in reset so will never decrement + chisel3.assert(reg === 6.U) + val (_, done) = Counter(true.B, 4) + when (done) { stop() } + }) + } "withClockAndReset" should "return like a normal Scala block" in { elaborate(new BasicTester { |
