diff options
| author | Jim Lawson | 2016-10-24 10:31:26 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-10-24 10:31:26 -0700 |
| commit | b0b5fd3140186651eb558bd6f4ca51c618deacc9 (patch) | |
| tree | 1393bbb14303af86aeb5e5ed0375f302864b8307 /src/test/scala/chiselTests/MultiAssign.scala | |
| parent | 82625071405672eb4a19363d6f73f359ac28a7f5 (diff) | |
| parent | 5df30b390ae5817c4793c6d4e0c5466d96d241f1 (diff) | |
Merge branch 'master' into tobits-deprecation
Diffstat (limited to 'src/test/scala/chiselTests/MultiAssign.scala')
| -rw-r--r-- | src/test/scala/chiselTests/MultiAssign.scala | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala index fa4c4898..397ea4c2 100644 --- a/src/test/scala/chiselTests/MultiAssign.scala +++ b/src/test/scala/chiselTests/MultiAssign.scala @@ -9,7 +9,8 @@ import chisel3.testers.BasicTester import chisel3.util._ class LastAssignTester() extends BasicTester { - val cnt = Counter(2) + val countOnClockCycles = Bool(true) + val (cnt, wrap) = Counter(countOnClockCycles,2) val test = Wire(UInt.width(4)) assert(test === 7.U) // allow read references before assign references @@ -20,7 +21,7 @@ class LastAssignTester() extends BasicTester { test := 7.U assert(test === 7.U) // this obviously should work - when(cnt.value === 1.U) { + when(cnt === 1.U) { stop() } } |
