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authorSchuyler Eldridge2020-06-22 20:34:46 -0400
committerGitHub2020-06-22 20:34:46 -0400
commit9f44b593efe4830aeb56d17f5ed59277a74832f8 (patch)
treeac43010dd7fc2a14303497f95e12f2a40bb16d0e /src/test/scala/chiselTests/MultiAssign.scala
parentd099d01ae6b11d8befdf7b32ab74c3167a552984 (diff)
parentb5e59895e13550006fd8e951b7e9483de00f82dd (diff)
Merge pull request #1481 from freechipsproject/driver-deprecations
Remove Deprecated Usages of chisel3.Driver, CircuitForm
Diffstat (limited to 'src/test/scala/chiselTests/MultiAssign.scala')
-rw-r--r--src/test/scala/chiselTests/MultiAssign.scala43
1 files changed, 30 insertions, 13 deletions
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index 8da5bc42..b232bd75 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -4,6 +4,7 @@ package chiselTests
import chisel3._
import chisel3.testers.BasicTester
+import chisel3.stage.ChiselStage
import chisel3.util._
class LastAssignTester() extends BasicTester {
@@ -30,36 +31,52 @@ class MultiAssignSpec extends ChiselFlatSpec {
}
}
-class IllegalAssignSpec extends ChiselFlatSpec {
+class IllegalAssignSpec extends ChiselFlatSpec with Utils {
"Reassignments to literals" should "be disallowed" in {
intercept[chisel3.internal.ChiselException] {
- elaborate{ new BasicTester {
- 15.U := 7.U
- }}
+ extractCause[ChiselException] {
+ ChiselStage.elaborate{
+ new BasicTester {
+ 15.U := 7.U
+ }
+ }
+ }
}
}
"Reassignments to ops" should "be disallowed" in {
intercept[chisel3.internal.ChiselException] {
- elaborate{ new BasicTester {
- (15.U + 1.U) := 7.U
- }}
+ extractCause[ChiselException] {
+ ChiselStage.elaborate{
+ new BasicTester {
+ (15.U + 1.U) := 7.U
+ }
+ }
+ }
}
}
"Reassignments to bit slices" should "be disallowed" in {
intercept[chisel3.internal.ChiselException] {
- elaborate{ new BasicTester {
- (15.U)(1, 0) := 7.U
- }}
+ extractCause[ChiselException] {
+ ChiselStage.elaborate{
+ new BasicTester {
+ (15.U)(1, 0) := 7.U
+ }
+ }
+ }
}
}
"Bulk-connecting two read-only nodes" should "be disallowed" in {
intercept[chisel3.internal.ChiselException] {
- elaborate{ new BasicTester {
- (15.U + 1.U) <> 7.U
- }}
+ extractCause[ChiselException] {
+ ChiselStage.elaborate{
+ new BasicTester {
+ (15.U + 1.U) <> 7.U
+ }
+ }
+ }
}
}
}