diff options
| author | Richard Lin | 2016-11-21 13:44:26 -0800 |
|---|---|---|
| committer | GitHub | 2016-11-21 13:44:26 -0800 |
| commit | 3b4755716a74d4711efa3ce6799742479e17e80b (patch) | |
| tree | 56652eaa478d5dfd8cddfbe2795c0123d39d230d /src/test/scala/chiselTests/MultiAssign.scala | |
| parent | cd6eb41275381a4399a8a88c886110d276bb805c (diff) | |
| parent | 81e5d00d18a5ba9ae33c10219a270148002fc672 (diff) | |
Merge pull request #372 from ucb-bar/onetrueliteral
Standardize the One True Way of specifying literals
Diffstat (limited to 'src/test/scala/chiselTests/MultiAssign.scala')
| -rw-r--r-- | src/test/scala/chiselTests/MultiAssign.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala index 397ea4c2..fbe57da5 100644 --- a/src/test/scala/chiselTests/MultiAssign.scala +++ b/src/test/scala/chiselTests/MultiAssign.scala @@ -9,10 +9,10 @@ import chisel3.testers.BasicTester import chisel3.util._ class LastAssignTester() extends BasicTester { - val countOnClockCycles = Bool(true) + val countOnClockCycles = true.B val (cnt, wrap) = Counter(countOnClockCycles,2) - val test = Wire(UInt.width(4)) + val test = Wire(UInt(4.W)) assert(test === 7.U) // allow read references before assign references test := 13.U |