Merge branch 'master' into 3.5-release

1 files changed, 9 insertions, 9 deletions

diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index fb5d6986..4cb51feb 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -9,16 +9,16 @@ import chisel3.util._
 
 class LastAssignTester() extends BasicTester {
   val countOnClockCycles = true.B
-  val (cnt, wrap) = Counter(countOnClockCycles,2)
+  val (cnt, wrap) = Counter(countOnClockCycles, 2)
 
   val test = Wire(UInt(4.W))
-  assert(test === 7.U)  // allow read references before assign references
+  assert(test === 7.U) // allow read references before assign references
 
   test := 13.U
-  assert(test === 7.U)  // output value should be position-independent
+  assert(test === 7.U) // output value should be position-independent
 
   test := 7.U
-  assert(test === 7.U)  // this obviously should work
+  assert(test === 7.U) // this obviously should work
 
   when(cnt === 1.U) {
     stop()
@@ -27,7 +27,7 @@ class LastAssignTester() extends BasicTester {
 
 class MultiAssignSpec extends ChiselFlatSpec {
   "The last assignment" should "be used when multiple assignments happen" in {
-    assertTesterPasses{ new LastAssignTester }
+    assertTesterPasses { new LastAssignTester }
   }
 }
 
@@ -35,7 +35,7 @@ class IllegalAssignSpec extends ChiselFlatSpec with Utils {
   "Reassignments to literals" should "be disallowed" in {
     intercept[chisel3.internal.ChiselException] {
       extractCause[ChiselException] {
-        ChiselStage.elaborate{
+        ChiselStage.elaborate {
           new BasicTester {
             15.U := 7.U
           }
@@ -47,7 +47,7 @@ class IllegalAssignSpec extends ChiselFlatSpec with Utils {
   "Reassignments to ops" should "be disallowed" in {
     intercept[chisel3.internal.ChiselException] {
       extractCause[ChiselException] {
-        ChiselStage.elaborate{
+        ChiselStage.elaborate {
           new BasicTester {
             (15.U + 1.U) := 7.U
           }
@@ -59,7 +59,7 @@ class IllegalAssignSpec extends ChiselFlatSpec with Utils {
   "Reassignments to bit slices" should "be disallowed" in {
     intercept[chisel3.internal.ChiselException] {
       extractCause[ChiselException] {
-        ChiselStage.elaborate{
+        ChiselStage.elaborate {
           new BasicTester {
             (15.U)(1, 0) := 7.U
           }
@@ -71,7 +71,7 @@ class IllegalAssignSpec extends ChiselFlatSpec with Utils {
   "Bulk-connecting two read-only nodes" should "be disallowed" in {
     intercept[chisel3.internal.ChiselException] {
       extractCause[ChiselException] {
-        ChiselStage.elaborate{
+        ChiselStage.elaborate {
           new BasicTester {
             (15.U + 1.U) <> 7.U
           }