diff options
| author | Jim Lawson | 2016-07-20 17:08:55 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-07-20 17:08:55 -0700 |
| commit | 1fa57cc3f76bc3e5de7e6b943abe70becdcb2295 (patch) | |
| tree | 1cea032150aae31fdf7cb995b26724be4b0ceb38 /src/test/scala/chiselTests/MultiAssign.scala | |
| parent | 2dce378deda1cc33833eb378c89a1c5415817bae (diff) | |
More literal/width rangling.
Diffstat (limited to 'src/test/scala/chiselTests/MultiAssign.scala')
| -rw-r--r-- | src/test/scala/chiselTests/MultiAssign.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala index 2399267e..fa4c4898 100644 --- a/src/test/scala/chiselTests/MultiAssign.scala +++ b/src/test/scala/chiselTests/MultiAssign.scala @@ -11,7 +11,7 @@ import chisel3.util._ class LastAssignTester() extends BasicTester { val cnt = Counter(2) - val test = Wire(UInt(width=4)) + val test = Wire(UInt.width(4)) assert(test === 7.U) // allow read references before assign references test := 13.U |