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| author | Jack Koenig | 2021-01-21 22:50:12 -0800 |
|---|---|---|
| committer | GitHub | 2021-01-21 22:50:12 -0800 |
| commit | dd6871b8b3f2619178c2a333d9d6083805d99e16 (patch) | |
| tree | 825776855e7d2fc28ef32ebb05df7339c24e00b3 /src/test/scala/chiselTests/Module.scala | |
| parent | 616256c35cb7de8fcd97df56af1986b747abe54d (diff) | |
| parent | 53c24cb0a369d4c4f57c28c098b30e4d3640eac2 (diff) | |
Merge pull request #1745 from chipsalliance/remove-val-io
Remove "val io" and rename MultiIOModule to Module
Diffstat (limited to 'src/test/scala/chiselTests/Module.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Module.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 03239785..932c94a5 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -143,7 +143,7 @@ class ModuleSpec extends ChiselPropSpec with Utils { property("DataMirror.modulePorts should work") { ChiselStage.elaborate(new Module { val io = IO(new Bundle { }) - val m = Module(new chisel3.MultiIOModule { + val m = Module(new chisel3.Module { val a = IO(UInt(8.W)) val b = IO(Bool()) }) |