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| author | Richard Lin | 2016-06-28 10:38:25 -0700 |
|---|---|---|
| committer | GitHub | 2016-06-28 10:38:25 -0700 |
| commit | bc3813ebd752646a92987c74136bb2adb476b687 (patch) | |
| tree | cc6e0e257f57d87e828a811e8c0c85d5780bb141 /src/test/scala/chiselTests/Module.scala | |
| parent | 3eb51f8484ad21d8a39da1ab7b036f1bb3bbe102 (diff) | |
| parent | a367073eaad494e86883b319d3b06bd6e8f05a00 (diff) | |
Merge pull request #224 from ucb-bar/renamechisel3
renamechisel3 - "chisel" -> "chisel3"
Diffstat (limited to 'src/test/scala/chiselTests/Module.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Module.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 64b00fab..23788b72 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -2,7 +2,7 @@ package chiselTests -import chisel._ +import chisel3._ class SimpleIO extends Bundle { val in = UInt(INPUT, 32) |