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| author | Jiuyang Liu | 2021-05-06 16:20:09 +0000 |
|---|---|---|
| committer | Jiuyang Liu | 2021-06-16 10:32:04 +0800 |
| commit | 3a74d433560c8aca8bf9b2734a3ee620a3442117 (patch) | |
| tree | 95d8cc74edb1dafcf7ebf694319da097bee8e1cc /src/test/scala/chiselTests/Module.scala | |
| parent | b0c76525ed53c20dbbe4bd8eea4a9676d7247ec7 (diff) | |
use z3 formal check minimized circuit and reference model.
Diffstat (limited to 'src/test/scala/chiselTests/Module.scala')
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