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| author | Jack Koenig | 2021-01-20 13:46:48 -0800 |
|---|---|---|
| committer | Jack Koenig | 2021-01-21 15:36:55 -0800 |
| commit | 5ece5aa8ac2716d66a6ed91e38a978049d8bf250 (patch) | |
| tree | f83353530e836491bb9b770712f1b8ff3dac3942 /src/test/scala/chiselTests/Module.scala | |
| parent | 616256c35cb7de8fcd97df56af1986b747abe54d (diff) | |
Rename MultiIOModule to Module
Diffstat (limited to 'src/test/scala/chiselTests/Module.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Module.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 03239785..932c94a5 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -143,7 +143,7 @@ class ModuleSpec extends ChiselPropSpec with Utils { property("DataMirror.modulePorts should work") { ChiselStage.elaborate(new Module { val io = IO(new Bundle { }) - val m = Module(new chisel3.MultiIOModule { + val m = Module(new chisel3.Module { val a = IO(UInt(8.W)) val b = IO(Bool()) }) |