From 5ece5aa8ac2716d66a6ed91e38a978049d8bf250 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 20 Jan 2021 13:46:48 -0800
Subject: Rename MultiIOModule to Module

---
 src/test/scala/chiselTests/Module.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/test/scala/chiselTests/Module.scala')

diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 03239785..932c94a5 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -143,7 +143,7 @@ class ModuleSpec extends ChiselPropSpec with Utils {
   property("DataMirror.modulePorts should work") {
     ChiselStage.elaborate(new Module {
       val io = IO(new Bundle { })
-      val m = Module(new chisel3.MultiIOModule {
+      val m = Module(new chisel3.Module {
         val a = IO(UInt(8.W))
         val b = IO(Bool())
       })
-- 
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