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authorducky2016-11-17 13:01:03 -0800
committerducky2016-11-21 13:31:12 -0800
commit54d3f8dc054e55dfbd01d1aa034169a3dabe89f2 (patch)
tree7f6f9de04de6eb08878ac46be339fefc2a71395f /src/test/scala/chiselTests/MemorySearch.scala
parentcd904da0aa0e96ba679906a3ee5dbdc068eace48 (diff)
Restyle a lot of test code, mainly with regex
Diffstat (limited to 'src/test/scala/chiselTests/MemorySearch.scala')
-rw-r--r--src/test/scala/chiselTests/MemorySearch.scala14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index 1d09f3c5..befbf010 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -7,21 +7,21 @@ import chisel3.testers.BasicTester
class MemorySearch extends Module {
val io = IO(new Bundle {
- val target = Input(UInt.width(4))
+ val target = Input(UInt(4.W))
val en = Input(Bool())
val done = Output(Bool())
- val address = Output(UInt.width(3))
+ val address = Output(UInt(3.W))
})
val vals = Array(0, 4, 15, 14, 2, 5, 13)
- val index = Reg(init = UInt(0, width = 3))
+ val index = Reg(init = 0.U(3.W))
val elts = Vec(vals.map(UInt(_,4)))
- // val elts = Mem(UInt(width = 32), 8) TODO ????
+ // val elts = Mem(UInt(32.W), 8) TODO ????
val elt = elts(index)
- val end = !io.en && ((elt === io.target) || (index === UInt(7)))
+ val end = !io.en && ((elt === io.target) || (index === 7.U))
when (io.en) {
- index := UInt(0)
+ index := 0.U
} .elsewhen (!end) {
- index := index +% UInt(1)
+ index := index +% 1.U
}
io.done := end
io.address := index