Merge pull request #2246 from chipsalliance/scalafmt

Add scalafmt configuration and apply it.

1 files changed, 12 insertions, 12 deletions

diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index ebfdace1..df1c6b32 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -7,23 +7,23 @@ import chisel3.stage.ChiselStage
 
 class MemorySearch extends Module {
   val io = IO(new Bundle {
-    val target  = Input(UInt(4.W))
-    val en      = Input(Bool())
-    val done    = Output(Bool())
+    val target = Input(UInt(4.W))
+    val en = Input(Bool())
+    val done = Output(Bool())
     val address = Output(UInt(3.W))
   })
-  val vals  = Array(0, 4, 15, 14, 2, 5, 13)
+  val vals = Array(0, 4, 15, 14, 2, 5, 13)
   val index = RegInit(0.U(3.W))
-  val elts  = VecInit(vals.map(_.asUInt(4.W)))
+  val elts = VecInit(vals.map(_.asUInt(4.W)))
   // val elts  = Mem(UInt(32.W), 8) TODO ????
-  val elt  = elts(index)
-  val end  = !io.en && ((elt === io.target) || (index === 7.U))
-  when (io.en) {
+  val elt = elts(index)
+  val end = !io.en && ((elt === io.target) || (index === 7.U))
+  when(io.en) {
     index := 0.U
-  } .elsewhen (!end) {
+  }.elsewhen(!end) {
     index := index +% 1.U
   }
-  io.done    := end
+  io.done := end
   io.address := index
 }
 
@@ -46,7 +46,7 @@ class MemorySearchTester(c: MemorySearch) extends Tester(c) {
            "LOOKING FOR " + target + " FOUND " + addr)
   }
 }
-*/
+ */
 
 class MemorySearchSpec extends ChiselPropSpec {
 
@@ -54,5 +54,5 @@ class MemorySearchSpec extends ChiselPropSpec {
     ChiselStage.elaborate { new EnableShiftRegister }
   }
 
-  ignore("MemorySearch should return the correct result") { }
+  ignore("MemorySearch should return the correct result") {}
 }