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| author | mergify[bot] | 2022-05-27 22:06:36 +0000 |
|---|---|---|
| committer | GitHub | 2022-05-27 22:06:36 +0000 |
| commit | 3aed65709aedc22810926751db33fe9ba767a03b (patch) | |
| tree | 28ac9216744c6f2315311674bf87a42846c69289 /src/test/scala/chiselTests/Mem.scala | |
| parent | 2453ac10fae363455398dd1ef5bcdb79e6d23f27 (diff) | |
Make ExtModule port naming consistent with Module (#2548) (#2549)
ExtModule now uses the same namePorts implementation as regular Modules.
Previously, ExtModules only allowed port naming via runtime reflection.
This meant that .suggestName and other naming APIs do not work. It also
breaks FlatIO for ExtModule which is a potential replacement API for
BlackBox's special `val io` handling.
(cherry picked from commit 83cccfb782d9141bf2c843246c2a525c62392924)
Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'src/test/scala/chiselTests/Mem.scala')
0 files changed, 0 insertions, 0 deletions